We are using this chip for voltage translate between 3.3V and 1.8V. The 1.8V side is not going to ground. What would be the likely cause of this?
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We are using this chip for voltage translate between 3.3V and 1.8V. The 1.8V side is not going to ground. What would be the likely cause of this?
Thanks! You have guided me to what most likely is the problem. The 1.8V section is split to a slide switch to be either a UART or I2C communication and there are pullup resistors present during UART communications. The I2C part of it works fine but not the UART.
I thought I might have had pullups in line but it turns out they are not populated. Here is the schematic as the pull up is happening on pin 15.
Show everything that is connected to UART_FTDI_TX.
Pins 1A2 and 2B2 must not be left open.
Hey Alan,
Thanks for the schematic. There are a couple items that I have questions/comments on:
First one comment - don't leave CMOS inputs floating. For your system, I'd recommend to pull-down 1A2 and 2B2 -- assuming you never change directions for 1DIR and 2DIR.
My main question is: what's connected at UART_FTDI_TX? From the scope shot, you have bus contention on that line (I am also assuming this is the line you showed previously -- it's the only one that makes sense).
My guess, from the schematic and your previous comments is that the UART driver is forcing the line high, and the AVC device is only able to pull it to about 1V.
Given that the output of the AVC device's output at 1.8V has a resistance around 30 ohms, we can easily calculate the required resistance to pull the line down to 1V using the voltage divider equation: Vout = Vin*R1/(R1+R2):
1V = 1.8V * 30/(30+R2) --> R2 = 24 ohms
While this is an estimate, it's pretty clear that there's something actively driving that line high -- it's not a dead short, nor is it a pull-up resistor.
Leaving pins open will result in extra power consumption and reduction in reliability (more details here), but it won't drag an adjacent channel down like this.
Are your TX/RX connections flipped intentionally here? That would be a good explanation of why there's bus contention.
Are you really sure that S4 is off?
Please show everything connected to G5_I2C2_SCL.