SN74LV8154-EP: Reading while counting

Part Number: SN74LV8154-EP
Other Parts Discussed in Thread: SN74LV8154

Hello Guys,

Good day.

Customer have the SN74LV8154 running nicely, but the question is if he run it at high speed like 5MHz or higher and when he is reading the counter while still counting, would that itself jeopardise the accuracy?

Or does the IC has its way of dealing with both with no problem? They have no way of comparing their result at this stage and hence the question.

Thanks in advance!


  • The storage register is separate from the counters. A rising edge on RCLK creates a snapshot of the counters, which can be read later.

    Please note the setup time: CLKA/CLKB and RCLK must not happen at the same time.

  • The customer have the RCLK, CLKA & CLKB tied together for a single 32Bit counter. What do you mean by setup time must not happen at the same time? Do he need to disconnect the RCLK during read time from input pulses?
    Kindly help to clarify.



  • Hi Art,

    Clemens is referring to the timing requirements section of the datasheet (see snippet below). The t_su parameter simply means that you'll need to wait at least 13ns after the rising edge of CLKA or CLKB before pulling RCLK high. From the info I have so far, yes, I'd recommend the customer separate these signals.


    Chad Crosby