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SN74LV8154-EP: Reading while counting

Art Mecina
Genius 16585 points
Part Number: SN74LV8154-EP
Other Parts Discussed in Thread: SN74LV8154

Hello Guys,

Good day.

Customer have the SN74LV8154 running nicely, but the question is if he run it at high speed like 5MHz or higher and when he is reading the counter while still counting, would that itself jeopardise the accuracy?

Or does the IC has its way of dealing with both with no problem? They have no way of comparing their result at this stage and hence the question.

Thanks in advance!

Art

  • 0
    Guru 269580 points

    The storage register is separate from the counters. A rising edge on RCLK creates a snapshot of the counters, which can be read later.

    Please note the setup time: CLKA/CLKB and RCLK must not happen at the same time.

  • 0 in reply to Clemens Ladisch
    TI__Genius 16585 points

    The customer have the RCLK, CLKA & CLKB tied together for a single 32Bit counter. What do you mean by setup time must not happen at the same time? Do he need to disconnect the RCLK during read time from input pulses?
    Kindly help to clarify.

    Regards,

    Art

  • 0 in reply to Art Mecina
    TI__Expert 6680 points

    Hi Art,

    Clemens is referring to the timing requirements section of the datasheet (see snippet below). The t_su parameter simply means that you'll need to wait at least 13ns after the rising edge of CLKA or CLKB before pulling RCLK high. From the info I have so far, yes, I'd recommend the customer separate these signals.

    Thanks!

    Chad Crosby

  • 0 in reply to Chad Crosby
    TI__Genius 16585 points

    Hello Chad,

    The customer now separated the RCLK from CLKA and B.

    When it says "CLKA or CLKB before pulling RCLK high" how do he know what state the CLKA is, plus, it is pulsing at high frequency and he only need the RCLK for 1ms or shorter, so surely it is not easy to tell or get it before CLKA? Or maybe he can minimize the RCLK to minimize the risk, I.e. 1uS instead of 1mS?

    Thanks and regards,

    Art

  • 0 in reply to Art Mecina
    TI__Guru* 96681 points

    Hi Art, 

    Art Mecina said:
    how do he know what state the CLKA is

    I'm a bit confused -- how is the customer generating the CLKA and CLKB signals without knowing their state?

    Art Mecina said:
    he only need the RCLK for 1ms or shorter, so surely it is not easy to tell or get it before CLKA?

    It sounds like he's just randomly changing RCLK without any concern for the timing for CLKA and CLKB. Is this the case?  If it is, it sounds like a probability problem rather than an engineering problem (ie there's a % chance of failure that can't be controlled with this method).

    The correct way to do this is to properly align your signals by running everything off the same clock signal -- you could use a flip-flop to synchronize the RCLK to the clock if the two signals are not directly linked otherwise.

  • 0 in reply to Emrys Maier
    TI__Genius 16585 points

    Hello Emrys,

    Please see below response from the customer in verbatim:

    "CLKA & CLKB are shorted together and attached is my pulse input that varies from 1Hz to 20MHz. I have no way of knowing their status and don't need to know.
    Are you suggesting to maybe use an AND gate to the CLKA from my Micro's O/P to RCLK, so this way the RCLK only gets activated when the CLKA is at a known state?
    Is that a common practice for cases where we want to read counter while still counting?"

    Thanks and regards,

    Art

  • 0 in reply to Art Mecina
    TI__Guru* 96681 points

    Honestly, I've never seen a case where an engineer was designing a synchronous logic circuit with unknown input constraints.

  • 0 in reply to Emrys Maier
    TI__Genius 16585 points

    Hi Emrys,

    A follow-up inquiry from the customer. To get accurate counts from this chip is to not interrupt it and then read it once finished counting? If that is the case then he mentioned he can use it for energy metering counting pulses.

    Best regards,
    Art

  • 0 in reply to Art Mecina
    TI__Guru* 96681 points

    Hi Art,

    Art Mecina said:
    To get accurate counts from this chip is to not interrupt it and then read it once finished counting?

    To get an accurate count, the device should be reset before starting the count (resets all internal registers to zero), then the input signal should meet all the requirements in the datasheet (VIH, VIL, ∆t/∆v) to ensure all pulses are counted.

    Driving RCLK high will trigger the device to store the current count in the register for later reading.

    The count stored in the storage register will be whatever was in the counter up to 13ns prior to the RCLK rising edge trigger.  So long as no count pulses have been received in the last 13ns, the stored count will be accurate.