HALCOGEN: Why doesn't HALCoGen generate source code for DMM

Andrew Harrington

Intellectual 445 points

Part Number: HALCOGEN
Other Parts Discussed in Thread: TMS570LC4357,

Hello,

I am using HALCoGen to generate code for a Hercules TMS570LC4357.

I want to use the DMM for GIO.

I can see that HALCoGen generates HL_dmm.h and HL_reg_dmm.h but it does not generate a HL_dmm.c.

I can see that HALCoGen generates various configuration values e.g. DMM_PC0_CONFIGVALUE

But how is DMM_PC0_CONFIGVALUE used to configure the Hercules?

Is the configuration of the DMM for GIO done by dmmInit()?

If so, then, where is dmmInit(), does it have to be written by hand?

Thank you.

over 4 years ago

0 Andrew Harrington over 4 years ago

Intellectual 445 points

Similar to above, does rtpInit() also have to be implemented by hand?

+1 QJ Wang over 4 years ago in reply to Andrew Harrington

TI__Guru**** 196776 points

Hi Andrew,

The HALCoGen doesn't generate code for several modules which are grayed in HalCoGen diagram. For example, DMM, RTP, HTU, FTU, Flexray, EPC, etc.

+1 QJ Wang over 4 years ago in reply to QJ Wang

TI__Guru**** 196776 points

I posted example code for DMM and RTP at the following thread:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/708846/tms570lc4357-hl_rtp-c-and-hl_dmm-c-missing-from-halcogen-generated-files/2612708?tisearch=e2e-sitesearch&keymatch=DMM.c#2612708

0 Andrew Harrington over 4 years ago in reply to QJ Wang

Intellectual 445 points

Hello QJ,

Thank you for the link.

However,when I click on either 3343.rtp.c or 2705.dmm.c I get the following message:

"You do not have permission to view this directory or page."

What do I need to do to access these files?

Regards,

Andrew

0 Andrew Harrington over 4 years ago in reply to QJ Wang

Intellectual 445 points

Hello QJ,

Thank you for the link.

However,when I click on either 3343.rtp.c or 2705.dmm.c I get the following message:

"You do not have permission to view this directory or page."

What do I need to do to access these files?

Regards,

Andrew

0 Andrew Harrington over 4 years ago in reply to QJ Wang

Intellectual 445 points

Hello QJ,

Thank you for the link.

However,when I click on either 3343.rtp.c or 2705.dmm.c I get the following message:

"You do not have permission to view this directory or page."

What do I need to do to access these files?

Regards,

Andrew

0 QJ Wang over 4 years ago in reply to Andrew Harrington

TI__Guru**** 196776 points

Hi Andrew,

I will find the files and re-post later. Thanks

+1 QJ Wang over 4 years ago in reply to QJ Wang

TI__Guru**** 196776 points

Fullscreen 5050.dmm.c Download

/** @file dmm.c 
*   @brief DMM Driver Implementation File
*   @date 9.Sep.2014
*   @version 04.01.00
*
*/

/* (c) Texas Instruments 2009-2014, All rights reserved. */

/* USER CODE BEGIN (0) */
/* USER CODE END */

#include "dmm.h"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/** @fn void dmmInit(void)
*   @brief Initializes the DMM Driver
*
*   This function initializes the DMM module.
*/
/* SourceId : DMM_SourceId_001 */
/* DesignId : DMM_DesignId_001 */
/* Requirements: HL_SR351 */
void dmmInit(void)
{

/* USER CODE BEGIN (2) */
/* USER CODE END */

    /** @b intalise @b DMM */

    /** @b initialize @b DMM @b Port */
    dmmREG->PC3 = (uint32)0U            /* DMM SYNC */
                | (uint32)((uint32)0U << 1U)     /* DMM CLK */
                | (uint32)((uint32)0U << 2U)     /* DATA[0] */
                | (uint32)((uint32)0U << 3U)     /* DATA[1] */
                | (uint32)((uint32)0U << 4U)     /* DATA[2] */
                | (uint32)((uint32)0U << 5U)     /* DATA[3] */
                | (uint32)((uint32)0U << 6U)     /* DATA[4] */
                | (uint32)((uint32)0U << 7U)     /* DATA[5] */
                | (uint32)((uint32)0U << 8U)     /* DATA[6] */
                | (uint32)((uint32)0U << 9U)     /* DATA[7] */
                | (uint32)((uint32)0U << 10U)   /* DATA[8] */
                | (uint32)((uint32)0U << 11U)   /* DATA[9] */
                | (uint32)((uint32)0U << 12U)   /* DATA[10] */
                | (uint32)((uint32)0U << 13U)   /* DATA[11] */
                | (uint32)((uint32)0U << 14U)   /* DATA[12] */
                | (uint32)((uint32)0U << 15U)   /* DATA[13] */
                | (uint32)((uint32)0U << 16U)   /* DATA[14] */
                | (uint32)((uint32)0U << 17U)   /* DATA[15] */
                | (uint32)((uint32)0U << 18U);  /* DMM ENA */

    /** - DMM Port direction */
    dmmREG->PC1 = (uint32) 1U             /* DMM SYNC */
                | (uint32)((uint32)1U << 1U)      /* DMM CLK */
                | (uint32)((uint32)1U << 2U)      /* DATA[0] */
                | (uint32)((uint32)1U << 3U)      /* DATA[1] */
                | (uint32)((uint32)0U << 4U)      /* DATA[2] */
                | (uint32)((uint32)1U << 5U)      /* DATA[3] */
                | (uint32)((uint32)1U << 6U)      /* DATA[4] */
                | (uint32)((uint32)0U << 7U)      /* DATA[5] */
                | (uint32)((uint32)0U << 8U)      /* DATA[6] */
                | (uint32)((uint32)1U << 9U)      /* DATA[7] */
                | (uint32)((uint32)1U << 10U)    /* DATA[8] */
                | (uint32)((uint32)0U << 11U)    /* DATA[9] */
                | (uint32)((uint32)0U << 12U)    /* DATA[10] */
                | (uint32)((uint32)1U << 13U)    /* DATA[11] */
                | (uint32)((uint32)1U << 14U)    /* DATA[12] */
                | (uint32)((uint32)0U << 15U)    /* DATA[13] */
                | (uint32)((uint32)0U << 16U)    /* DATA[14] */
                | (uint32)((uint32)1U << 17U)    /* DATA[15] */
                | (uint32)((uint32)1U << 18U);   /* DMM ENA */
                
    /** - DMM Port open drain enable */
    dmmREG->PC6 = (uint32) 0U             /* DMM SYNC */
                | (uint32)((uint32)0U << 1U)      /* DMM CLK */
                | (uint32)((uint32)0U << 2U)      /* DATA[0] */
                | (uint32)((uint32)0U << 3U)      /* DATA[1] */
                | (uint32)((uint32)0U << 4U)      /* DATA[2] */
                | (uint32)((uint32)0U << 5U)      /* DATA[3] */
                | (uint32)((uint32)0U << 6U)      /* DATA[4] */
                | (uint32)((uint32)0U << 7U)      /* DATA[5] */
                | (uint32)((uint32)0U << 8U)      /* DATA[6] */
                | (uint32)((uint32)0U << 9U)      /* DATA[7] */
                | (uint32)((uint32)0U << 10U)    /* DATA[8] */
                | (uint32)((uint32)0U << 11U)    /* DATA[9] */
                | (uint32)((uint32)0U << 12U)    /* DATA[10] */
                | (uint32)((uint32)0U << 13U)    /* DATA[11] */
                | (uint32)((uint32)0U << 14U)    /* DATA[12] */
                | (uint32)((uint32)0U << 15U)    /* DATA[13] */
                | (uint32)((uint32)0U << 16U)    /* DATA[14] */
                | (uint32)((uint32)0U << 17U)    /* DATA[15] */
                | (uint32)((uint32)0U << 18U);   /* DMM ENA */

    /** - DMM Port pullup / pulldown selection */
    dmmREG->PC8 = (uint32) 1U             /* DMM SYNC */
                | (uint32)((uint32)1U << 1U)      /* DMM CLK */
                | (uint32)((uint32)1U << 2U)      /* DATA[0] */
                | (uint32)((uint32)1U << 3U)      /* DATA[1] */
                | (uint32)((uint32)1U << 4U)      /* DATA[2] */
                | (uint32)((uint32)1U << 5U)      /* DATA[3] */
                | (uint32)((uint32)1U << 6U)      /* DATA[4] */
                | (uint32)((uint32)1U << 7U)      /* DATA[5] */
                | (uint32)((uint32)1U << 8U)      /* DATA[6] */
                | (uint32)((uint32)1U << 9U)      /* DATA[7] */
                | (uint32)((uint32)1U << 10U)    /* DATA[8] */
                | (uint32)((uint32)1U << 11U)    /* DATA[9] */
                | (uint32)((uint32)1U << 12U)    /* DATA[10] */
                | (uint32)((uint32)1U << 13U)    /* DATA[11] */
                | (uint32)((uint32)1U << 14U)    /* DATA[12] */
                | (uint32)((uint32)1U << 15U)    /* DATA[13] */
                | (uint32)((uint32)1U << 16U)    /* DATA[14] */
                | (uint32)((uint32)1U << 17U)    /* DATA[15] */
                | (uint32)((uint32)1U << 18U);   /* DMM ENA */

    /** - DMM Port pullup / pulldown enable*/
    dmmREG->PC7 = (uint32) 0U           /* DMM SYNC */
                | (uint32)((uint32)0U << 1U)    /* DMM CLK */
                | (uint32)((uint32)0U << 2U)    /* DATA[0] */
                | (uint32)((uint32)0U << 3U)    /* DATA[1] */
                | (uint32)((uint32)0U << 4U)    /* DATA[2] */
                | (uint32)((uint32)0U << 5U)    /* DATA[3] */
                | (uint32)((uint32)0U << 6U)    /* DATA[4] */
                | (uint32)((uint32)0U << 7U)    /* DATA[5] */
                | (uint32)((uint32)0U << 8U)    /* DATA[6] */
                | (uint32)((uint32)0U << 9U)    /* DATA[7] */
                | (uint32)((uint32)0U << 10U)  /* DATA[8] */
                | (uint32)((uint32)0U << 11U)  /* DATA[9] */
                | (uint32)((uint32)0U << 12U)  /* DATA[10] */
                | (uint32)((uint32)0U << 13U)  /* DATA[11] */
                | (uint32)((uint32)0U << 14U)  /* DATA[12] */
                | (uint32)((uint32)0U << 15U)  /* DATA[13] */
                | (uint32)((uint32)0U << 16U)  /* DATA[14] */
                | (uint32)((uint32)0U << 17U)  /* DATA[15] */
                | (uint32)((uint32)0U << 18U); /* DMM ENA */

    /* DMM set all pins to functional */
    dmmREG->PC0 = (uint32) 1U           /* DMM SYNC */
                | (uint32)((uint32)1U << 1U)    /* DMM CLK */
                | (uint32)((uint32)1U << 2U)    /* DATA[0] */
                | (uint32)((uint32)1U << 3U)    /* DATA[1] */
                | (uint32)((uint32)1U << 4U)    /* DATA[2] */
                | (uint32)((uint32)1U << 5U)    /* DATA[3] */
                | (uint32)((uint32)1U << 6U)    /* DATA[4] */
                | (uint32)((uint32)1U << 7U)    /* DATA[5] */
                | (uint32)((uint32)1U << 8U)    /* DATA[6] */
                | (uint32)((uint32)1U << 9U)    /* DATA[7] */
                | (uint32)((uint32)1U << 10U)  /* DATA[8] */  
                | (uint32)((uint32)1U << 11U)  /* DATA[9] */  
                | (uint32)((uint32)1U << 12U)  /* DATA[10] */  
                | (uint32)((uint32)1U << 13U)  /* DATA[11] */  
                | (uint32)((uint32)1U << 14U)  /* DATA[12] */  
                | (uint32)((uint32)1U << 15U)  /* DATA[13] */  
                | (uint32)((uint32)1U << 16U)  /* DATA[14] */  
                | (uint32)((uint32)1U << 17U)  /* DATA[15] */  
                | (uint32)((uint32)1U << 18U); /* DMM ENA */  

/* USER CODE BEGIN (3) */
/* USER CODE END */

}

/** @fn void dmmGetConfigValue(dmm_config_reg_t *config_reg, config_value_type_t type)
*   @brief Get the initial or current values of the DMM configuration registers
*
*   @param[in] *config_reg: pointer to the struct to which the initial or current 
*                           value of the configuration registers need to be stored
*   @param[in] type:    whether initial or current value of the configuration registers need to be stored
*                       - InitialValue: initial value of the configuration registers will be stored 
*                                       in the struct pointed by config_reg
*                       - CurrentValue: initial value of the configuration registers will be stored 
*                                       in the struct pointed by config_reg
*
*   This function will copy the initial or current value (depending on the parameter 'type') 
*   of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : DMM_SourceId_002 */
/* DesignId : DMM_DesignId_002 */
/* Requirements: HL_SR352 */
void dmmGetConfigValue(dmm_config_reg_t *config_reg, config_value_type_t type)
{
    if (type == InitialValue)
    {
        config_reg->CONFIG_PC0 = DMM_PC0_CONFIGVALUE;
        config_reg->CONFIG_PC1 = DMM_PC1_CONFIGVALUE;
        config_reg->CONFIG_PC3 = DMM_PC3_CONFIGVALUE;
        config_reg->CONFIG_PC6 = DMM_PC6_CONFIGVALUE;
        config_reg->CONFIG_PC7 = DMM_PC7_CONFIGVALUE;
        config_reg->CONFIG_PC8 = DMM_PC8_CONFIGVALUE;
    }
    else
    {
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
        config_reg->CONFIG_PC0 = dmmREG->PC0;
        config_reg->CONFIG_PC1 = dmmREG->PC1;
        config_reg->CONFIG_PC3 = dmmREG->PC3;
        config_reg->CONFIG_PC6 = dmmREG->PC6;
        config_reg->CONFIG_PC7 = dmmREG->PC7; 
        config_reg->CONFIG_PC8 = dmmREG->PC8;
    }
}

Fullscreen 8473.rtp.c Download

/** @file rtp.c
*   @brief RTP Driver Implementation File
*   @date 9.Sep.2014
*   @version 04.01.00
*
*/

/* (c) Texas Instruments 2009-2014, All rights reserved. */

/* USER CODE BEGIN (0) */
/* USER CODE END */

#include "rtp.h"

/* USER CODE BEGIN (1) */
/* USER CODE END */

/** @fn void rtpInit(void)
*   @brief Initializes the RTP Driver
*
*   This function initializes the RTP module.
*/
/* SourceId : RTP_SourceId_001 */
/* DesignId : RTP_DesignId_001 */
/* Requirements : HL_SR347 */
void rtpInit(void)
{

/* USER CODE BEGIN (2) */
/* USER CODE END */

    /** @b intalise @b RTP */

    /** @b initialize @b RTP @b Port */

    /** - RTP Port output values */
    rtpREG->PC3 = (uint32) 0U            /* DATA[0] */
                | (uint32)((uint32)0U << 1U)     /* DATA[1] */
                | (uint32)((uint32)0U << 2U)     /* DATA[2] */
                | (uint32)((uint32)0U << 3U)     /* DATA[3] */
                | (uint32)((uint32)0U << 4U)     /* DATA[4] */
                | (uint32)((uint32)0U << 5U)     /* DATA[5] */
                | (uint32)((uint32)0U << 6U)     /* DATA[6] */
                | (uint32)((uint32)0U << 7U)     /* DATA[7] */
                | (uint32)((uint32)0U << 8U)     /* DATA[8] */
                | (uint32)((uint32)0U << 9U)     /* DATA[9] */
                | (uint32)((uint32)0U << 10U)   /* DATA[10] */
                | (uint32)((uint32)0U << 11U)   /* DATA[11] */
                | (uint32)((uint32)0U << 12U)   /* DATA[12] */
                | (uint32)((uint32)0U << 13U)   /* DATA[13] */
                | (uint32)((uint32)0U << 14U)   /* DATA[14] */
                | (uint32)((uint32)0U << 15U)   /* DATA[15] */
                | (uint32)((uint32)0U << 16U)   /* RTP SYNC */
                | (uint32)((uint32)0U << 17U)   /* RTP CLK */
                | (uint32)((uint32)0U << 18U);  /* RTP ENA */

    /** - RTP Port direction */
    rtpREG->PC1 = (uint32) 1U             /* DATA[0] */
                | (uint32)((uint32)1U << 1U)      /* DATA[1] */
                | (uint32)((uint32)1U << 2U)      /* DATA[2] */
                | (uint32)((uint32)1U << 3U)      /* DATA[3] */
                | (uint32)((uint32)0U << 4U)      /* DATA[4] */
                | (uint32)((uint32)1U << 5U)      /* DATA[5] */
                | (uint32)((uint32)1U << 6U)      /* DATA[6] */
                | (uint32)((uint32)0U << 7U)      /* DATA[7] */
                | (uint32)((uint32)0U << 8U)      /* DATA[8] */
                | (uint32)((uint32)1U << 9U)      /* DATA[9] */
                | (uint32)((uint32)1U << 10U)    /* DATA[10] */
                | (uint32)((uint32)0U << 11U)    /* DATA[11] */
                | (uint32)((uint32)0U << 12U)    /* DATA[12] */
                | (uint32)((uint32)1U << 13U)    /* DATA[13] */
                | (uint32)((uint32)1U << 14U)    /* DATA[14] */
                | (uint32)((uint32)0U << 15U)    /* DATA[15] */
                | (uint32)((uint32)0U << 16U)    /* RTP SYNC */
                | (uint32)((uint32)1U << 17U)    /* RTP CLK */
                | (uint32)((uint32)1U << 18U);   /* RTP ENA */

    /** - RTP Port open drain enable */
    rtpREG->PC6 = (uint32) 0U             /* DATA[0] */
                | (uint32)((uint32)0U << 1U)      /* DATA[1] */
                | (uint32)((uint32)0U << 2U)      /* DATA[2] */
                | (uint32)((uint32)0U << 3U)      /* DATA[3] */
                | (uint32)((uint32)0U << 4U)      /* DATA[4] */
                | (uint32)((uint32)0U << 5U)      /* DATA[5] */
                | (uint32)((uint32)0U << 6U)      /* DATA[6] */
                | (uint32)((uint32)0U << 7U)      /* DATA[7] */
                | (uint32)((uint32)0U << 8U)      /* DATA[8] */
                | (uint32)((uint32)0U << 9U)      /* DATA[9] */
                | (uint32)((uint32)0U << 10U)    /* DATA[10] */
                | (uint32)((uint32)0U << 11U)    /* DATA[11] */
                | (uint32)((uint32)0U << 12U)    /* DATA[12] */
                | (uint32)((uint32)0U << 13U)    /* DATA[13] */
                | (uint32)((uint32)0U << 14U)    /* DATA[14] */
                | (uint32)((uint32)0U << 15U)    /* DATA[15] */
                | (uint32)((uint32)0U << 16U)    /* RTP SYNC */
                | (uint32)((uint32)0U << 17U)    /* RTP CLK */
                | (uint32)((uint32)0U << 18U);   /* RTP ENA */

    /** - RTP Port pullup / pulldown selection */
    rtpREG->PC8 = (uint32) 1U             /* DATA[0] */
                | (uint32)((uint32)1U << 1U)      /* DATA[1] */
                | (uint32)((uint32)1U << 2U)      /* DATA[2] */
                | (uint32)((uint32)1U << 3U)      /* DATA[3] */
                | (uint32)((uint32)1U << 4U)      /* DATA[4] */
                | (uint32)((uint32)1U << 5U)      /* DATA[5] */
                | (uint32)((uint32)1U << 6U)      /* DATA[6] */
                | (uint32)((uint32)1U << 7U)      /* DATA[7] */
                | (uint32)((uint32)1U << 8U)      /* DATA[8] */
                | (uint32)((uint32)1U << 9U)      /* DATA[9] */
                | (uint32)((uint32)1U << 10U)    /* DATA[10] */
                | (uint32)((uint32)1U << 11U)    /* DATA[11] */
                | (uint32)((uint32)1U << 12U)    /* DATA[12] */
                | (uint32)((uint32)1U << 13U)    /* DATA[13] */
                | (uint32)((uint32)1U << 14U)    /* DATA[14] */
                | (uint32)((uint32)1U << 15U)    /* DATA[15] */
                | (uint32)((uint32)1U << 16U)    /* RTP SYNC */
                | (uint32)((uint32)1U << 17U)    /* RTP CLK */
                | (uint32)((uint32)1U << 18U);   /* RTP ENA */

    /** - RTP Port pullup / pulldown enable*/
    rtpREG->PC7 = (uint32) 0U            /* DATA[0] */
                | (uint32)((uint32)0U << 1U)     /* DATA[1] */
                | (uint32)((uint32)0U << 2U)     /* DATA[2] */
                | (uint32)((uint32)0U << 3U)     /* DATA[3] */
                | (uint32)((uint32)0U << 4U)     /* DATA[4] */
                | (uint32)((uint32)0U << 5U)     /* DATA[5] */
                | (uint32)((uint32)0U << 6U)     /* DATA[6] */
                | (uint32)((uint32)0U << 7U)     /* DATA[7] */
                | (uint32)((uint32)0U << 8U)     /* DATA[8] */
                | (uint32)((uint32)0U << 9U)     /* DATA[9] */
                | (uint32)((uint32)0U << 10U)   /* DATA[10] */
                | (uint32)((uint32)0U << 11U)   /* DATA[11] */
                | (uint32)((uint32)0U << 12U)   /* DATA[12] */
                | (uint32)((uint32)0U << 13U)   /* DATA[13] */
                | (uint32)((uint32)0U << 14U)   /* DATA[14] */
                | (uint32)((uint32)0U << 15U)   /* DATA[15] */
                | (uint32)((uint32)0U << 16U)   /* RTP SYNC */
                | (uint32)((uint32)0U << 17U)   /* RTP CLK */
                | (uint32)((uint32)0U << 18U);  /* RTP ENA */

    /* RTP set all pins to functional */
    rtpREG->PC0 = (uint32) 1U             /* DATA[0] */
                | (uint32)((uint32)1U << 1U)      /* DATA[1] */
                | (uint32)((uint32)1U << 2U)      /* DATA[2] */
                | (uint32)((uint32)1U << 3U)      /* DATA[3] */
                | (uint32)((uint32)1U << 4U)      /* DATA[4] */
                | (uint32)((uint32)1U << 5U)      /* DATA[5] */
                | (uint32)((uint32)1U << 6U)      /* DATA[6] */
                | (uint32)((uint32)1U << 7U)      /* DATA[7] */
                | (uint32)((uint32)1U << 8U)      /* DATA[8] */
                | (uint32)((uint32)1U << 9U)      /* DATA[9] */
                | (uint32)((uint32)1U << 10U)    /* DATA[10] */
                | (uint32)((uint32)1U << 11U)    /* DATA[11] */
                | (uint32)((uint32)1U << 12U)    /* DATA[12] */
                | (uint32)((uint32)1U << 13U)    /* DATA[13] */
                | (uint32)((uint32)1U << 14U)    /* DATA[14] */
                | (uint32)((uint32)1U << 15U)    /* DATA[15] */
                | (uint32)((uint32)1U << 16U)    /* RTP SYNC */
                | (uint32)((uint32)1U << 17U)    /* RTP CLK */
                | (uint32)((uint32)1U << 18U);   /* RTP ENA */

/* USER CODE BEGIN (3) */
/* USER CODE END */

}


/** @fn void rtpGetConfigValue(rtp_config_reg_t *config_reg, config_value_type_t type)
*   @brief Get the initial or current values of the RTP configuration registers
*
*	@param[in] *config_reg: pointer to the struct to which the initial or current 
*                           value of the configuration registers need to be stored
*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
*						- InitialValue: initial value of the configuration registers will be stored 
*                                       in the struct pointed by config_reg
*						- CurrentValue: initial value of the configuration registers will be stored 
*                                       in the struct pointed by config_reg
*
*   This function will copy the initial or current value (depending on the parameter 'type') 
*   of the configuration registers to the struct pointed by config_reg
*
*/
/* SourceId : RTP_SourceId_002 */
/* DesignId : RTP_DesignId_002 */
/* Requirements : HL_SR348 */
void rtpGetConfigValue(rtp_config_reg_t *config_reg, config_value_type_t type)
{
	if (type == InitialValue)
	{
		config_reg->CONFIG_PC0 = RTP_PC0_CONFIGVALUE;
		config_reg->CONFIG_PC1 = RTP_PC1_CONFIGVALUE;
		config_reg->CONFIG_PC3 = RTP_PC3_CONFIGVALUE;
		config_reg->CONFIG_PC6 = RTP_PC6_CONFIGVALUE;
		config_reg->CONFIG_PC7 = RTP_PC7_CONFIGVALUE;
		config_reg->CONFIG_PC8 = RTP_PC8_CONFIGVALUE;
	}
	else
	{
	/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
		config_reg->CONFIG_PC0 = rtpREG->PC0;
		config_reg->CONFIG_PC1 = rtpREG->PC1;
		config_reg->CONFIG_PC3 = rtpREG->PC3;
		config_reg->CONFIG_PC6 = rtpREG->PC6;
		config_reg->CONFIG_PC7 = rtpREG->PC7; 
		config_reg->CONFIG_PC8 = rtpREG->PC8;
	}
}

0 Andrew Harrington over 4 years ago in reply to QJ Wang

Intellectual 445 points

Hi QJ,

Thank you for your assistance.

Andrew

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