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Hello TI
What is the effect/behavior of the half duplex setting (register SPIFMTx, bit HDUPLEX_ENAx=1) in the 4-line parallel mode (SPIPMCTRL.PMODEx=2)? The SPI will be MibSPI5 in Master mode.
The manual says that the HDUPLEX_ENAx “controls the I/O function of SOMI/SIMO lines…”. In the 4-bit parallel mode, there are 4 SIMO lines. Does the half duplex setting switch all of them? If not, which lines are used for data input (and output)?
The background for this question is that we need to implement Quad SPI. I understood from other answers on this forum that it is not natively supported on this CPU, and we are looking for solutions that do not involve the other 4 SOMI lines, as the Quad SPI is half-duplex anyway.
Thank you,
Josef
Hi Josef,
There is no data in TRM to support "working of Half duplex in parallel mode".
But when i verified old e2e threads i found below thread, which is handled by my senior colleague.
TMDX570LC43HDK: TMS 570 MIBSPI slave not receiving data - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums
If you see the last comments in above thread,
there he clearly mentioned that Half duplex will not work for MibSPIP(MibSPI parallel mode).
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Thanks,
Jagadish.
