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MCU-PLUS-SDK-AM243X: SBL_OSPI works only when started after SoC initialization script but it fails when starting from flash

Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: AM2434, SYSCONFIG, UNIFLASH

Hi, I am just using your fresh released SDK  mcu_plus_sdk_am243x_08_03_00_18 with our custom board based on AM2434.

I have prepared and tested your SPL_OSPI bootloader example on a EMMC flash filled with an application starting at 0x80000.

So my steps were:

  • loading the SoC initialization script with CCS version 1120
  • loading the spl_ospi bootloader (I removed the line Bootloader_socWaitForFWBoot since the SysFW was already loaded)
  • I could see my application successfully started

Later on I wanted to flash the spl_ospi bootloader at the beginning of EMMC flash, so I used the SPL_JTAG bootloader just after SoC initialization script.

Unexpectedly the SPL_OSPI bootloader flashed on EMMC coudn't run !
It fails on Board_driversOpen(); because the EMMC flash is unreadable.

I found the issue is in flash_nor_xspi.c then it tries to read the attack vector in OSPI_phyReadAttackVector.

In order to debug the issue I reflashed the SPL_OSPI bootloader with loop_forever() just before Board_driversOpen() so I could connect the debugger and load the symbols.

After OSPI_enableDacMode(handle) in OSPI_phyReadAttackVector in source\drivers\ospi\v0\ospi_phy.c, I tried to inspect the EMMC content with memory browser: I've just found zeros.

BUT -----------------

If I continue to start the same code just after SoC Initialization script, instead of flashing on EMMC, it works !

The previous SDK 08.02.00.31 isn't affected by this issue and the SPL_OSPI bootloader could successfully run either after SoC initialization script or directly from EMMC

How about SysFw or BlobConfiguration ?

Looking forward

   Andrea

  • Hi Andrea,

    To help me understand your problem better, please let me know the following details:

    1. In your custom board, are you using a NOR SPI flash tied to the OSPI IP? Or eMMC? Because SBL OSPI is meant for NOR SPI flashes only. Furthermore, the SBL which ships with the SDK is supposed to work for the OSPI flash in the AM243x EVM (S28HS512T) or AM243x LP (S25HL512T). These are selectable from the sysconfig of SBL OSPI. If you want to support a custom flash, there is a procedure to add that to the SDK - https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_03_00_18/exports/docs/api_guide_am243x/CUSTOM_FLASH_SUPPORT_GUIDE.html . Since your flow works in 8.2 SDK, I assume you have the right flash.

    2. The attackVector is supposed to be flashed to the flash device already at the last block's address. The UART based flashing tool has an option to do this, the SBL JTAG doesn't have this option. This is required if you want to have PHY enabled for the OSPI driver. Is there any hurdle regarding using the UART based flashing tool? ( we even have an experimental GUI for this - find the usage link here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/08_03_00_18/exports/docs/api_guide_am243x/TOOLS_FLASH.html#TOOLS_UART_UNIFLASH_GUI
    If you don't want to try this, you can disable the PHY in SBL OSPI's sysconfig and see SBL OSPI goes through.

    Let me know if writing the attackVector (or disabling PHY if that is not possible) helped you get past the Board_driversOpen().

    Also, when you're booting the SBL OSPI directly, keep the Bootloader_socWaitForFWBoot line since it takes 12-13 ms for the SYSFW to initialize and send the boot notification and SBL shouldn't start System_init before that.

    Regards,
    Anand M

  • Hi Anand,

       in our custom board we are using  NOR SPI flash of the same type as in your demo board AM243x EVM, so S28HS512T.

    At my opinion the problem isn't in the attackVector self, but it is the first reading that the driver is doing at Board_driversOpen().

    Here is my test ospi bootloader initiatization part:

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    int main()
    {
    int32_t status;
    volatile int32_t count = 0;
    volatile register int32_t resetForJtag = 0;
    volatile register int32_t startFromCCS = 0;
    volatile register int32_t waitForDebugger = 1;
    Bootloader_profileReset();
    if (!startFromCCS) {
    Bootloader_socWaitForFWBoot();
    }
    Bootloader_profileAddProfilePoint("SYSFW init");
    Bootloader_socOpenFirewalls();
    System_init();
    Bootloader_profileAddProfilePoint("System_init");
    Drivers_open();
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    I wanted to test exactely the same code running from flash or from CCS initialization script.

    My breakpoint is at line 483 in C:\ti\mcu_plus_sdk_am243x_08_03_00_18\source\board\flash\flash_nor_xspi.c

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    /* Enable PHY if attack vector present and PHY mode is enabled */
    /*>>>*/ uint32_t phyTuningOffset = Flash_getPhyTuningOffset(config);
    if(OSPI_isPhyEnable(obj->ospiHandle))
    {
    attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
    if(attackVectorStatus != SystemP_SUCCESS)
    {
    /* Flash the attack vector to the last block */
    uint32_t blk = 0, page = 0;
    uint32_t phyTuningData = 0,phyTuningDataSize = 0;
    OSPI_phyGetTuningData(&phyTuningData, &phyTuningDataSize);
    Flash_offsetToBlkPage(config, phyTuningOffset, &blk, &page);
    Flash_norXspiErase(config, blk);
    Flash_norXspiWrite(config, phyTuningOffset, (uint8_t *)phyTuningData, phyTuningDataSize);
    attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
    }
    if(attackVectorStatus == SystemP_SUCCESS)
    {
    status += OSPI_phyTuneDDR(obj->ospiHandle, phyTuningOffset);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    1) CASE RUNNING FROM CCS

    Our board is always set in OSPI boot mode but we can disable the flash power with a switch to let the ROM code to fallback in NoBoot mode.

    • I set the switch to disable flash power supply
    • I turn POWER ON
    • I use loadJs from CCS script console to initializate SysFw
    • I set the switch to enable flash power supply
    • I load my ospi bootloader
    • I set variable startFromCCS to 1 in order to skip Bootloader_socWaitForFWBoot()
    • I set variable waitForDebugger to 0 in order to don't wait into the while loop
    • I set a breakpoint at line 483 in flash_nor_xspi.c
    • When the execution flow passes from
                attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
      it will read successfully the attackVector and attackVectorStatus will become zero

    2) CASE RUNNING FROM FLASH

    I used JTAG uniflash tool to flash ospi bootloader debug tiimage at the beginning of the flash (offset 0x0).

    Our board doesn't have a UART (in production version) so jtag is the only way to connect to when the flash is empty.

    • I set the switch to enable flash power supply
    • I turn POWER ON
    • I start a debug session in CCS and I connect to the R5 core 0-0
    • I load the symbols
    • I find the debugger stopped at the while loop, so I set the variable waitForDebugger to 0 in order to exit
    • I set a breakpoint at line 483 in flash_nor_xspi.c
    • When the execution flow passes from
                attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);
      it will fail and attackVectorStatus will become -1
    • The code execution will continue trying to write into the last block of the flash a new attackVector
    • Then in the code there is a new call trying to read the attackVector just written and it fails again !

    I hope this can help you to discover which is the reason why the flash seams not readable in case 2.

    Previous SDK 08.02.00.31 isn't affected by this issue and ospi bootloader runs from flash like a charm.

    Looking forward

        Andrea

  • Hi Anand,

      any news about this issue ?

    Looking forward

       Andrea

  • I've just discovered the issue and it was related to OSPI RSTn pin.
    I've changed the sysconfig template file in ospi_init.c.xdt in order to have our flash chip out of reset.

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    #ifdef OSPI_RSTN_PIN
    GPIO_setDirMode(OSPI_RSTN_BASE_ADDR, OSPI_RSTN_PIN, OSPI_RSTN_DIR);
    GPIO_pinWriteHigh(OSPI_RSTN_BASE_ADDR, OSPI_RSTN_PIN);
    #endif
    OSPI_init();
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    So when I set the GPIO pin direction as output, the output register is still zero causing a reset of the flash hardware.

    If I do reverse, so forcing output value first and then pin direction I prevent the spurious reset.

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    #ifdef OSPI_RSTN_PIN
    GPIO_pinWriteHigh(OSPI_RSTN_BASE_ADDR, OSPI_RSTN_PIN);
    GPIO_setDirMode(OSPI_RSTN_BASE_ADDR, OSPI_RSTN_PIN, OSPI_RSTN_DIR);
    #endif
    OSPI_init();
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Actually it isn't clear why it worked when loading the ospi bootloader after SOC initialization by CCS script