TMS570LC4357: t_WDELAY depending on CSHOLD?

Hello experts,

Timing measurements during hardware commissioning revealed, that the measured CS inactive time for short CS inactive pulses is one VCLK cycle shorter than expected from the TRM.

The VCLK frequency is set to 75 MHz. --> VCLK period is 1 / (75 MHz) = 13.3333 ns.

SPI configuration parameters:

• SPIGCR1.MASTER = 1 and SPIGCR1.CLKMOD = 1. --> TMS570 is master.
• SPIDEF.CSDEF = 1 for the relevant CS. --> SPICS is set to 1 when no transfer is active, i.e. CS is an active-Low signal.
• SPIFMTx.PRESCALE = 74. --> The selected MibSPI clock frequency is 1 MHz.
• SPIFMTx.POLARITY = 1, SPIFMTx.PHASE = 0. --> SPI clock signal is High-inactive. The first data bit is transmitted with the first clock edge and the first bit is received with the second (inverse) clock edge. As POLARITY is set to 1, output data transitions occur on the falling edge of the SPI clock. Input data is captured on the rising edge of the SPI clock. This is referred to as Mode 3.
• SPIFMTx.DIS_CS_TIMERS = 0. --> Both C2TDELAY and T2CDELAY counts are inserted for the chip-selects.
• SPIFMTx.WAITENA = 0. --> The SPI does not wait for the ENA signal from the slave and directly starts the transfer.
• WDEL is set to 1 for every TXRAM entry.
• SPIFMTx.WDELAY = 5. --> Expected wait delay between transmissions is (5 + 2) / fVCLK = 93.3333 ns, but 80 ns were measured.

For several WDELAY settings, it was checked with the oscilloscope, that the observed deviation is not a tolerance issue caused by slow CS edges. CS inactive pulse duration “+Width”:

Further investigations have shown that the CS High pulse duration depends on the CSHOLD bit. It was observed, that the CS inactive pulse duration is one VCLK cycle shorter than expected from the TRM, when CSHOLD = 1 for the subsequent SPI transmission. CSHOLD = 1 does not introduce an additional VCLK cycle between CS activation and first CLK edge, but it shortens the CS inactive pulse by 1 VCLK cycle, so that the additional VCLK cycle between CS activation and first CLK edge (refer to datasheet  § 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications) is only one effect to be observed. The more critical (and so far undocumented!?!) effect is the shortening of the CS inactive pulse duration by one VCLK cycle.

The following timing diagram was recorded with a sample rate of 1.6 GS/s. The CSHOLD bit was varied for the SPI transactions. This leads to different duration of the CS High pulse.

The CS pulse width at cursor A is too short, whereas the CS pulse width at cursor D is correct. The CS pulse width at curser C is correct, whereas the CS pulse width at cursor E is too short.
--> A too short CS pulse width is generated when CSHOLD = 0 is followed by CSHOLD = 1. A correct CS pulse width is generated when CSHOLD = 0 is followed by CSHOLD = 0.
From a functional point of view, it makes no sense that the CS inactive state is terminated one VCLK cycle earlier than configured, when the SW requests CS to remain active after the SPI transmission.

Questions:

1. Is the described topic known at TI? If yes, can you please provide a reference (erratum number, application note etc.)?
2. Can you please confirm, that for CSHOLD=0 the chip-select inactive pulse is at least as long as documented in the TRM? (I.e. the issue only occurs for CSHOLD=1, not for CSHOLD=0?)
3. Any suggestions on how to handle this issue now?

Thank you.