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We are trying to send multiple words over an SPI interface using TMS570LS20216 MCU. In C language, we set the CSHOLD bit of DAT1 register separately, and then write the TXDATA field afterwards.
We have inspected the assembler instructions used to set the CSHOLD bit. In the C code, we have defined the register fields as C struct bit fields. The C compiler (Keil uVision 4.54.0.0) generates STRB (store byte) instructions to modify only the byte of interest within the DAT1 register.
We observe that when a STRB instruction is executed to store the high order byte of the DAT1 register with the CSHOLD bit set to 0, the nCS line IMMEDIATELY transitions from low to high, thus ending the SPI transaction. We also observe that when CSHOLD is set to 1 using the same method, the nCS line IMMEDIATELY transitions to low rather than waiting until the transmission. In both these cases, the low-order 16 bits of DAT1 (the TXDATA field) is untouched. This is further proved by the fact that no clock is generated when modifying the CSHOLD bit alone. The clock is generated when the TXDATA field written using a STRH (store have word) instruction.
After reading the datasheet, we would have expected the nCS line to change (or not) AFTER the next transaction, not immediately upon setting or clearing CSHOLD. Is this an error in the silicon? It is perhaps a bit unclear from the datasheet whether this is supported.
