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[FAQ] TMS570LS1224: When reading from Flash ECC space or SRAM ECC space, does a double-bit error detected generate data abort?

QJ Wang
Guru**** 192196 points
Part Number: TMS570LS1224

The Hercules microcontrollers protect all accesses to the on-chip flash memory and on-chip SRAM memory by dedicated Single-Error-Correction-Double-Error-Detection (SECDED) logic. The access to the program memory (bank 0 or bank 1) and SRAM is protected by SECDED logic implemented inside the ARM Cortex-R4F CPU. Accesses to the EEPROM emulation flash bank (bank 7) are protected by dedicated SECDED logic inside the flash wrapper. 

1. ECC Memory Space for BTCM Interface is 0x0840_0000. During Cortex-R4 read access from ECC BTCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

2. ECC Memory Space for ATCM Interface is 0xF040_0000. During Cortex-R4 read access from ECC ATCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

3. ECC Memory Space for EEPROM Bank7 Interface is 0xF010_0000. During Cortex-R4 read access from ECC Bank 7 Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

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    TI__Guru**** 192196 points
    QJ Wang said:
    1. ECC Memory Space for BTCM Interface is 0x0840_0000. During Cortex-R4 read access from ECC BTCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

    Yes, you will get an abort if CPU detects an double bit error when reading from the ECC BTCM space. When reading from the ECC space, the data is actually the ECC. So what is returned to the CPU is an 8-bit ECC value repeated 8 times on the 64-bit data bus plus again the same 8-bit ECC value on the 8-bit ECC bus. This pair of data and ECC can result in a syndrome that can be beyond SECDED's capability in which case it can be interpreted as no error or single bit error or double error. 

    QJ Wang said:
    2. ECC Memory Space for ATCM Interface is 0xF040_0000. During Cortex-R4 read access from ECC ATCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

    The ATCM (main flash) ECC Memory space is at 0xF040_0000. Reading from 0xF040_0000 happens on the Cortex-R4's AXI bus. This AXI read transaction will get routed to the flash wrapper Bus2 interface. There is no built-in ECC checking capability on the Cortex-R4 on its AXI bus interface. So first of all, the Cortex-R4 will not perform any ECC checking when reading from ATCM ECC space. Therefore, it does not know if there is fault in the data. No abort will be generated and neither the data fault status and address registers are updated. The flash wrapper will perform the ECC checking on this bus2 access. If there is a double bit error detected it will be signaled to the ESM.

    The flash bank is 144-wide which contains two 64-bit data and two 8-bit ECC respectively. This is read at once by the flash wrapper. Even though that you are reading the ATCM ECC space from the CPU's memory map point of view (at 0xF040_0000), the flash wrapper actually reads also the corresponding 64-bit data which is mapped to 0x0000_0000. If there is a valid data at 0x0000_0000 and its corresponding ECC then there will not be any error detected when reading from the ECC space unless you intentionally inject some fault to cause ECC error. If you read from an ECC space location for which it's corresponding data is not populated with data or code then you can get an ECC error. Example would be reading from a location that has both the data and ECC being all F's.

    QJ Wang said:
    3. ECC Memory Space for EEPROM Bank7 Interface is 0xF010_0000. During Cortex-R4 read access from ECC Bank 7 Space, if there is a Double Bit Error detected by Cortex-R4, will there be a data abort?

    Same answer as #2.