BTCM ECC Space Read will generate ABORT from Cortex-R4

Hello Pashan,

1> ECC Detection inside Cortex-R4 core is always ENABLED

  ECC Detection by default after reset is disabled. User needs to enable it by setting bit[27:25] of the auxiliary control register.

2> ECC Correction can be DISABLED within Cortex-R4 Core

 Yes, once the ECC checking is enabled, the correction can be disabled using bit[3:2] of the secondary auxiliary control register. But if you get a single bit correctable error you wll get an abort. Uncorrectable errors always generate abort.

3> Double-Bit ECC Fault detection within Cortex-R4 core will generate ABORT [DATA or PREFETCH]

Yes.

4> In the snippet below, it says that for RAM ECC Memory Space Read from BTCM Interface by Cortex-R4, there will be no ECC Error on TCRAM Interface

  The note actually says "This could result in the detection of a mult-bit error by the SECDED logic inside the CPU". What is intendted to be read by the CPU is just the ECC value. There is no proper ECC checksum for the ECC value itself. The CPU can result in any type of error among no error, single bit error, double bit error or multiple bit error. Note that SECDED breaks down when there are multi-bit error as it can't reliably detects more than two bit error.

regards,

Charles

Hello Pashan,

1> ECC Memory Space for BTCM Interface is 0x0840_0000. During Cortex-R4 read access from ECC BTCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be an ABORT?

 Yes, you will get an abort if CPU detects an double bit error when reading from the ECC BTCM space. Note that as I mentioned it the earlier reply the CPU may not 100% of time detects it as a double bit error resulting in an abort. It all depends on the data + ECC pair. In the case of reading from the ECC space, the data is actually the ECC. So what is returned to the CPU is an 8-bit ECC value repeated 8 times on the 64-bit data bus plus again the same 8-bit ECC value on the ECC in-band bus. This pair of data and ECC can result in a syndrome that can be beyond SECDED's capability in which case it can be interpreted as no error or single bit error or double error. 

2> ECC Memory Space for ATCM Interface is 0xF040_0000. During Cortex-R4 read access from ECC ATCM Space, if there is a Double Bit Error detected by Cortex-R4, will there be an ABORT?

As you pointed out, the ATCM ECC Memory space is at 0xF040_0000. This is NOT an access from the ATCM. Reading from 0xF040_0000 happens on the Cortex-R4's AXI bus. This AXI read transaction will get routed to the flash wrapper Bus2 interface. There is no built-in ECC checking capability on the Cortex-R4 on its AXI bus interface. So first of all, the Cortex-R4 will not perform any ECC checking when reading from ATCM ECC space. Therefore, it does not know if there is fault in the data. No abort will be generated and neither the data fault status and address registers are updated. The flash wrapper will perform the ECC checking on this bus2 access. If there is a double bit error detected it will be signaled to the ESM.

One note I want to make here is that the flash bank is 144-wide which contains two 64-bit data and two 8-bit ECC respectively. This is read at once by the flash wrapper. Even though that you are reading the ATCM ECC space from the CPU's memory map point of view (at 0xF040_0000), the flash wrapper actually reads also the corresponding 64-bit data which is mapped to 0x0000_0000. If there is a valid data at 0x0000_0000 and its corresponding ECC then there will not be any error detected when reading from the ECC space unless you intentionally inject some fault to cause ECC error. If you read from an ECC space location for which it's corresponding data is not populated with data or code then you can get an ECC error. Example would be reading from a location that has both the data and ECC being all F's.

3> ECC Memory Space for FLEE Bank7 Interface is 0xF010_0000. During Cortex-R4 read access from ECC FLEE Bank 7 Space, if there is a Double Bit Error detected by Cortex-R4, will there be an ABORT?

Same answer as #2.