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TMS570LS1224: ADC generated DMA requests

Simon Metzger
Prodigy 30 points
Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello TI-Support

I set up the ADC module with the HET1 as conversion trigger - this works fine so far. Now I would like to use DMA to transfer the ADC-results into a buffer.

I would like to configure the DMA Request for a fixed number of conversion results.

To this end I set the G1DMACR register as follows:

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adcREG1->G1DMACR = (uint32)((uint32)0x18 << 16U) | (uint32)((uint32)1U << 2U);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

My intention is to set the G1_BLOCKS to 0x18 (24), to generate a DMA group transfer request every 24 conversions.

However, it seems that a DMA-request is generated ever 8 conversions.

What am I doing wrong here?

  • 0
    TI__Guru 63035 points

    Hi Simon,

    I hope you enabled the Group-1 DMA transfer

    And i also would like to know how you are confirming DMA-request generation after 8 conversions? is it based on number of converted values moved in DMA destination buffer?

    I also need DMA side configuration you did, like Frame count, Element count etc.

    --

    Thanks & Regards,

    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 30 points

    Hello Jagadish

    I set Bit 2 (G1_BLK_XFER) of the G1DMACR.

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    adcREG1->G1DMACR = (uint32)((uint32)0x18 << 16U) | (uint32)((uint32)1U << 2U);
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    According to the technical_reference manual: "Group1 Block DMA Transfer Enable. If G1 BLK_XFER bit is set to 1, G1_DMA_EN bit is ignored and DMA requests are generated every time the Threshold Counter reaches 0 from a count value of 1.

    Therefore, I thought I do not need to set G1_DMA_EN.

    Also, the dma transfer works but the transfer is requested every 8 conversions instead of every 24 conversions.

    I configured the ADC1-memory in HalCoGen, I dont need the EventGroup and Group2.

    Here is the DMA-Side configuration:

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    g_dmaCTRLPKT_ADC1.SADD = (uint32)&adcREG1->GxBUF[0].BUF0 + 2; /* source address: EvBuffer1 + 2 Bytes offset */
    g_dmaCTRLPKT_ADC1.DADD = (uint32)&ADC1DataA[0]; /* destination address, start with Buffer A */
    g_dmaCTRLPKT_ADC1.CHCTRL = 0; /* next channel to be chained, 0 = disable chaining */
    g_dmaCTRLPKT_ADC1.FRCNT = 1; /* frame count, number of ADC samples */
    g_dmaCTRLPKT_ADC1.ELCNT = 24; /* element count, number of ADC channels */
    g_dmaCTRLPKT_ADC1.ELDOFFSET = 0; /* element destination offset to be added after each element transfer in number of bytes*/
    g_dmaCTRLPKT_ADC1.ELSOFFSET = 4; /* element source offset to be added after each element transfer in number of bytes */
    g_dmaCTRLPKT_ADC1.FRDOFFSET = 0; /* frame destination offset to be added after the count reaches zero in number of bytes */
    g_dmaCTRLPKT_ADC1.FRSOFFSET = 0; /* frame source offset to be added after the count reaches zero in number of bytes */
    g_dmaCTRLPKT_ADC1.PORTASGN = 4; /* dma port b, always 0x100 for all TMS570 */
    g_dmaCTRLPKT_ADC1.RDSIZE = ACCESS_16_BIT; /* read size ToDo: tbd */
    g_dmaCTRLPKT_ADC1.WRSIZE = ACCESS_16_BIT; /* write size */
    g_dmaCTRLPKT_ADC1.TTYPE = BLOCK_TRANSFER; /* transfer type */
    g_dmaCTRLPKT_ADC1.ADDMODERD = ADDR_OFFSET; /* address mode read */
    g_dmaCTRLPKT_ADC1.ADDMODEWR = ADDR_INC1; /* address mode write */
    g_dmaCTRLPKT_ADC1.AUTOINIT = AUTOINIT_ON; /* autoinit */
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Simon Metzger
    TI__Guru 63035 points

    Hi Simon,

    Simon Metzger said:
    Therefore, I thought I do not need to set G1_DMA_EN.

    You are right and this is not required.

    Thank you for sharing DMA configuration details, i am trying trigger same issue at my end and i will give update to you as soon as possible.

    --
    Thanks & Regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    TI__Guru 63035 points

    Hi Simon,

    I understood the root cause for your problem, what is the below FIFO size you configured in your code?

    Maybe you configured 8 due to that the DMA trigger is occurring for every 8 conversions, you should configure above value as 24 to get DMA trigger for every 24 conversions.

    Also, in your DMA configuration you should make below changes

    The above changes required because we are reading from ADC FIFO right not directly from ADC RAM. So, we should not give reading address mode as OFFSET, read address should be fixed as we are reading from FIFO, after reading first converted value the second converted value will be shifted to the FIFO from RAM, so we no need to increment the reading address.

    --

    Thanks & Regards,

    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 30 points

    Dear Jagadish

    I changed the configurations as you suggested and now everything works fine.

    Thanks for your support!