TMS570LS1224: ADC with DMA (spna227)

xTaskHandle xUserTaskHandle;
void vUserTask(void *pvParameters)
{
    const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
    uint16_t n = 0;
    while (1)
    {
        adcStartConversion(adcREG1, adcGROUP1);

        for (n = 0; n < ADC_SAMPLE_COUNT; n++)
        {
            printf("[%u] Ch: %u, ADC: %u\n", n,
                                             (uint32)((adc1_G1_results[n] >> 16U) & 0x1FU),  // Channel ID
                                             (uint16)(adc1_G1_results[n] & 0xFFFU));         // Value
        }
        printf("----------------\n");

        vTaskDelay(xDelay);
    }
}

/* USER CODE END */
void main(void)
{
    /* USER CODE BEGIN (3) */
    gioInit();
    hetInit();
    esmInit();
    sciInit();
    sciEnableNotification(scilinREG, SCI_RX_INT);
    sciReceive(scilinREG, 1, &rx_byte);

    adcInit();
    adcREG1->G1DMACR = (1U << 0U) |                // G1_DMA_EN - ADC module generates a DMA transfer when the ADC has written to the Group1 memory. G1_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated.
                       (1U << 2U) |                // G1_BLK_XFER - ADC module generates a DMA request when the ADC has written G1_BLOCKS number of buffers into the Group1 memory.
                       (1U << 3U) |                // DMA_G1_END - ADC module generates a DMA request when the ADC has completed the conversions for all channels selected for conversion in the group1.
                       (ADC_SAMPLE_COUNT << 16U);  // G1_BLOCKS - One DMA request is generated if the G1_BLK_XFER is set to ‘1’ and the specified number of Group1 conversion results have been accumulated
                                                       // ADC_SAMPLE_COUNT = 32U, equal to the configured FIFO size inside HALCoGen
    // adcEnableNotification(adcREG1, adcGROUP1);

    dmaEnable();
    dmaReqAssign(1, 10);
    dmaConfigCtrlPacket(ADG1_ptr,                               // control packet for group1
                        (uint32)(&adcREG1->GxBUF[1]),           // group1 results FIFO
                        (uint32)(&adc1_G1_results),             // group1 results in CPU data RAM
                        ADC_SAMPLE_COUNT,                       // number of frames to be transferred
                        1,                                      // number of elements per frame
                        0,                                      // next channel to be chained, 0 = disable chaining
                        2,                                      // read element size (32 bits)
                        2,                                      // write element size (32 bits)
                        1,                                      // transfer type = 1 ==> block transfer
                        0,                                      // read addressing mode = 0 ==> fixed
                        1,                                      // write addressing mode = 1 ==> post-incremented
                        1,                                      // autoinit enabled
                        0,                                      // read address element index offset = 0
                        0,                                      // write address element index offset = 0
                        0,                                      // read address frame index offset = 0
                        0);                                     // write address frame index offset = 0

    dmaSetCtrlPacket(DMA_CH1, *ADG1_ptr);
    dmaSetChEnable(DMA_CH1, DMA_HW);
    // dmaEnableInterrupt(DMA_CH1, BTC);

    if(xTaskCreate(vUserTask, "UserTask", 512, NULL, tskIDLE_PRIORITY + 1, &xUserTaskHandle) != pdTRUE)
    {
        while (1);
    }

    _enable_IRQ();
    _enable_FIQ();

    vTaskStartScheduler();

    return;
    /* USER CODE END */
}

    #define ADC_SAMPLE_COUNT 32U // Equal to the configured FIFO size in HALCoGen
    
    ...

    adcREG1->G1DMACR = (1U << 0U) |                // G1_DMA_EN - ADC module generates a DMA transfer when the ADC has written to the Group1 memory. G1_BLK_XFER bit must be cleared to ‘0’ for this DMA request to be generated.
                       (1U << 2U) |                // G1_BLK_XFER - ADC module generates a DMA request when the ADC has written G1_BLOCKS number of buffers into the Group1 memory.
                       (1U << 3U) |                // DMA_G1_END - ADC module generates a DMA request when the ADC has completed the conversions for all channels selected for conversion in the group1.
                       (ADC_SAMPLE_COUNT << 16U);  // G1_BLOCKS - One DMA request is generated if the G1_BLK_XFER is set to ‘1’ and the specified number of Group1 conversion results have been accumulated
                                                       // ADC_SAMPLE_COUNT = 32U, equal to the configured FIFO size inside HALCoGen

----------------
[0] Ch: 6, ADC: 420
[1] Ch: 8, ADC: 0
[2] Ch: 8, ADC: 0
[3] Ch: 8, ADC: 0
[4] Ch: 8, ADC: 0
[5] Ch: 8, ADC: 0
[6] Ch: 8, ADC: 0
[7] Ch: 8, ADC: 0
[8] Ch: 8, ADC: 0
[9] Ch: 8, ADC: 0
[10] Ch: 8, ADC: 0
[11] Ch: 8, ADC: 0
[12] Ch: 8, ADC: 0
[13] Ch: 8, ADC: 0
[14] Ch: 8, ADC: 0
[15] Ch: 8, ADC: 0
[16] Ch: 8, ADC: 0
[17] Ch: 8, ADC: 0
[18] Ch: 8, ADC: 0
[19] Ch: 8, ADC: 0
[20] Ch: 8, ADC: 0
[21] Ch: 8, ADC: 0
[22] Ch: 8, ADC: 0
[23] Ch: 8, ADC: 0
[24] Ch: 8, ADC: 0
[25] Ch: 8, ADC: 0
[26] Ch: 8, ADC: 0
[27] Ch: 8, ADC: 0
[28] Ch: 8, ADC: 0
[29] Ch: 8, ADC: 0
[30] Ch: 8, ADC: 0
[31] Ch: 8, ADC: 0
----------------