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SPI Delayed Slave Data Receipt Sampling

Tony Morrell
Genius 4130 points

Hi,

I have a question regarding SPI receive sampling. I have a master and slave device connected via 4MHz SPI. This SPI connection has an in-line digital isolator on the signals which introduces a 70ns nominal delay is signal transmission. This means that the slave data received at the master is some 140ns nominal delayed (approximately 1/2 the 250ns cycle). This means that my slave data sampling at the master occurs approximately 1/2 a cycle too early.

Is there any way I can sample the slave data a full cycle from SPICLK driven SPISIMO, instead of the usual 1/2 cycle. So instead of (based on TRM 14-8 to show delayed slave data receive):

have this instead (modified from TRM 14-8, receive sample point shifted only):

 

Regards, Tony.

  • 0
    TI__Guru 68830 points

    Sorry Tony,

    We don't have support for this clocking mode option in the SPI;  just the typical four modes.

    You might need to use two SPI ports configured differently - each in a 'unidirectional' mode (from board standpoint).*

    Depending on what type of device is on the other side of your isolation chip there may be some other options to consider, but simple answer is the SPI doesn't have the mode you're asking about.

    Best Regards,
    Anthony 

    * I say from a board standpoint, because I believe with the SPI on these products if you don't enable at least the SPI SIMO, SOMI and CLK pins as SPI function rather than GPIO function, then no transmision will occur.

  • 0 in reply to Anthony F. Seely
    Genius 4130 points

    Thanks Anthony.

    The device on the other side of the digital isolator is another TMS570!

    We have found a higher spec digital isolator with a 27ns nominal delay, and so a round trip of some 54ns delay. This seems to work reliably at SPI transmission speeds of 4MHz.

    Regards, Tony.

  • 0 in reply to Tony Morrell
    TI__Guru 68830 points

    Hi Tony,

    Glad you were able to find a solution.   (Hopefully it's one of TI's ISOxxx parts ;) )

    Just for completeness in answering the post - If it's a 570 on the other side of the isolation then two things you might also consider could be:

      1.  Are you making use of the SPIENA\ pin?   Would it be possible to lower the clock rate by doing so?

           SPIENA\ provides a handshake signal back from the slave device that confirms its ready for the next transfer;  so the master doesn't have to insert a 'worst case' delay between transfers.   This might buy something in terms of clock speed reduction - although at the expense of another channel of isolator for the handshake signal.

      2.   Another way to lower the SPI clock rate would be to use the parallel SPI mode that's available on the TMS570.  If you were to move up to two data pins in each direction you might be able to cut the required clock rate down by say 30%  (won't be 50% because there is overhead between successive transfers).   Of course this would come at the expense of two extra isolation channels.

    Seems like what could have been perfect is if we had a 4Mbaud capable UART?

    Thanks and Best Regards,

    Anthony 

  • 0 in reply to Anthony F. Seely
    Genius 4130 points

    Hi Antony,

    Thanks for your suggestions. We need the 4Mbit/s to adequately transfer our data in the required time. We also have a requirement to minimise the number of SPI lines used, so we only use CLK, CS, MISO and MOSI. We are also using all three of the SPI modules, we need three independent lines of communication from each processor in our fault tolerant network.

    Regards, Tony.