TMS570LC4357: TMS570LC4357: Arbitration to access CPU SRAM between masters (New thread)

Hi,

The CPU Interconnect uses round-robin arbitration so no master blocks the other bus masters from accessing the SRAM. I don't see the following statement in DS and TRM:

"The CPU SRAM interconnect is designed such that an arbitration condition only exists if both the CPU and the DMA are accessing the same 64-bit address in the same cycle"

Hi,

https://en.wikipedia.org/wiki/Round-robin_scheduling

Does it mean DMA and CPU has a fix slice of time so that they cannot block each other if they access at the same time the SRAM? 

Thanks 

Mathieu 

Hi QJ Wang,

Look at your statement in the following thread. Where did you get the information about the arbitration on 64-bit address? 

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/886793/tms570ls1114-dma-and-cpu-bus-arbitration

Regards

Mathieu

Mathieu Quenpt said:

Does it mean DMA and CPU has a fix slice of time so that they cannot block each other if they access at the same time the SRAM? 

Yes, you are correct.

It would be very helpful if you can provide an answer to my second question.

"Look at your statement in the following thread. Where did you get the information about the arbitration on 64-bit address?"

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/886793/tms570ls1114-dma-and-cpu-bus-arbitration

Thank you very much! 

Hi Mathieu,

I am sorry for the confused statement. This statement only applies to TMS570LSx and RM4xLx Cortex-R4 based devices. TMS570LSx device htwo L1 memories: ATCM (flash) and BTCM (SRAM). The BTCM interface is divided into two parts: B0TCM and B1TCM, which are used to interface to two SRAM banks. BTCM0 is even address SRAM, and BTCM1 is odd address SRAM. The round-robin scheme is used by SCR to arbitrate masters' request.

The addresses on BTCM0/BTCM1 are interleaved by 64b word (even and odd). DMA can access BTCM0 while CPU is accessing BTCM1. 

Memory address      BTCM0       BTCM1

-------------------------------------------------------

0x0800_0000           X

0x0800_0008                                   X

0x0800_0010           X

0x0800_0018                                   X

0x0800_0020           X

0x0800_0028                                   X

0x0800_0030           X

0x0800_0038                                   X

......

Thanks for your answer!

In which cortex 5 user guide can I find the statement about the round-robin scheme? I could not find it in DDI0460D_cortex_r5_r1p2_trm

The device TRM mentions the round robin scheme.

Which revision number? I cannot find it in any TRM. Thanks

https://www.ti.com/lit/ug/spnu563a/spnu563a.pdf?ts=1670370826481&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTMS570LC4357

Thanks for the link! I am doing an analysis of the run-time in the worst-case. In my case, DMA and CPU access RAM parallelly. My question is: can CPU access to SRAM be blocked by DMA, if the slice allocated to the CPU to access the SRAM is not sufficient and get preempted from a DMA access to the SRAM due to the round-robin scheme?

Is there a precise description how the round-robin scheme work?

Thanks