Hi,
I am clumsy about the QSSI. My approach is to communicate with a quad simultaneous sampling ADC (by name AD7389-4) over SPI and use therefore the TM4C1294NCPDT MCU with TI-RTOS. I want to accumulate the data from the ADC at least for 3 channels at the same time.
Now I figured out that the approach isn't achievable because of the mentioned half-duplex mode at quad-SSI data transfer in the MCU Data Sheet at section 17.3.3 on page 1230 and the ADC expected full duplex. Moreover, the minimum required SCLK cycles are 16 for the ADC and the QSSI outside the SSI Legacy operation is only 8-bits packet data capable. Furthermore, the QSSI works as parallel interface for let's say 1 Byte, not parallel for multiple serial data lines. Am I right with these Acknowledgments?
Am I right that with my configuration, it is not possible to achieve a “full duplex” data transmission? It is not possible to set one QSSI data pin as TX and the remaining data pins as RX to communicate at least with 3 of the 4 channels from the ADC with at least 16-bits of packet data? Is there another way to achieve a simultaneous data transmission by another SW configuration of the QSSI with the mentioned HW configuration which I miss out? And to be clear, the goal to achieve this approach ends up in using a multi-core MCU like AM2434, some FPGA solution or reading all 4 channels via one SSIxTX and SSIxRX (full duplex) in Legacy SSI Mode?
Kind regards,
Daniel
