MCU-PLUS-SDK-AM243X: SDK 08.05/08.04 new Flash-Driver not functional with ISSI Flash

Felix Heil

Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: SYSCONFIG

Hello,

we tried updateing the SDK to 08.05 and postponed the new flash-driver in 08.04 already. So we wanted to finally update it but experiences problems as described in https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1189521/mcu-plus-sdk-am243x-loadcpus-sometimes-asserts-in-dma-access/4521992#4521992

with the IS25WX256T it does not seem to work, at least the read data is not correct.

I will copy the observation from the other thread:

so I compared the init of both sdks. First I let the old one run, which works. I copied all the issued flash-cmds for config inside Flash_norOspiOpen and copied the register values to compare them. The only difference I see is the order of the address-byte setting. But the registers seem to be the same in the end. I let both run until

attackVectorStatus = OSPI_phyReadAttackVector(obj->ospiHandle, phyTuningOffset);

since this is the point where we get different results when reading the flash.

Every indendation means this is the value/call inside the function above.

for the old working drivers:

Flash_norOspiReadId
  Flash_norOspiCmdRead(config, cmd(0x9F), cmdAddr(OSPI_CMD_INVALID_ADDR), numAddrBytes(0), idCode, numRdIdBytes(5))
  OSPI_setDeviceSize(obj->ospiHandle, attrs->pageSize, attrs->blockSize)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg	0x00111002	Device Size Configuration Register [Memory Mapped]	
OSPI_setCmdExtType(obj->ospiHandle, OSPI_CMD_EXT_TYPE_INVERSE)
  obj->cmdExtType = cmdExtType;
obj->dtrEnable = OSPI_isDtrEnable(obj->ospiHandle); (1)
OSPI_getXferLines(obj->ospiHandle) (3/OCTAL)
Flash_norOspiEnable4ByteAddr(config)
  Flash_norOspiCmdWrite(config, devDefines->NOR_CMD_WREN(0x06), OSPI_CMD_INVALID_ADDR, 0, NULL, 0)
  Flash_norOspiCmdWrite(config, devDefines->NOR_CMD_WRCR2(0x81), devDefines->NOR_ADDRESS_CONFIG_REG_ADDR(0x5), 3, &regData(0xFE), 1);
Flash_norOspiCmdWrite(config, ((Flash_NorOspiDevDefines *)config->devDefines)->NOR_CMD_4BEN(0xB7), OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
OSPI_setNumAddrBytes(obj->ospiHandle, 4)
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg	0x00111003	Device Size Configuration Register [Memory Mapped]	
Flash_norOspiEnableDDR(config)
  Flash_norOspiCmdWrite(config, devDefines->NOR_CMD_WREN(0x06), OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
  Flash_norOspiCmdWrite(config, devDefines->NOR_CMD_WRCR2(0x81), devDefines->NOR_DDR_EN_REG_ADDR(0), 4, &regData(0xE7), 1);
  OSPI_enableDDR(obj->ospiHandle)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0x81783801	Octal-SPI Configuration Register [Memory Mapped]	
obj->xferLines = OSPI_XFER_LINES_OCTAL;
Flash_norOspiSetOpcodes(config)
  readCmd     = devDefines->NOR_CMD_OCTAL_READ_DDR;
  progCmd     = devDefines->NOR_CMD_PAGE_PROG;
  OSPI_setXferLines(obj->ospiHandle, obj->xferLines);
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x00033303	Device Read Instruction Configuration Register [Memory Mapped]	
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg	0x00033002	Device Write Instruction Configuration Register [Memory Mapped]	
    obj->xferLines = xferLines;
  OSPI_setXferOpCodes(obj->ospiHandle, readCmd, progCmd)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x000333FD	Device Read Instruction Configuration Register [Memory Mapped]	
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg	0x02EDFA7A	Opcode Extension Register (Lower) [Memory Mapped]	
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg	0x00033012	Device Write Instruction Configuration Register [Memory Mapped]	
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg	0x02EDFA7A	Opcode Extension Register (Lower) [Memory Mapped]	
Flash_norOspiSetDummyCycles(config)
  OSPI_setReadDummyCycles(obj->ospiHandle, rdDummyCycles)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x100333FD	Device Read Instruction Configuration Register [Memory Mapped]	
  OSPI_setCmdDummyCycles(obj->ospiHandle, cmdDummyCycles)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg	0x810B8400	Flash Command Control Register [Memory Mapped]	
  OSPI_setDualOpCodeMode(obj->ospiHandle)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0xC1783801	Octal-SPI Configuration Register [Memory Mapped]	
  Flash_norOspiRegRead(config, devDefines->NOR_DUMMY_CYCLE_PROG_REG_ADDR(0x1), &regData(0x1F)
  Flash_norOspiRegWrite(config, devDefines->NOR_DUMMY_CYCLE_PROG_REG_ADDR, regData(0x10))
OSPI_setRdDataCaptureDelay(obj->ospiHandle, readDataCapDelay);
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg	0x00000127	Read Data Capture Register [Memory Mapped]	
OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0xC1783881	Octal-SPI Configuration Register [Memory Mapped]

for the new updated - not working - driver:

OSPI_setDeviceSize
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg	0x00111002	Device Size Configuration Register [Memory Mapped]
OSPI_setCmdExtType
  obj->cmdExtType = cmdExtType;
obj->numAddrBytes = 3;
obj->currentProtocol = FLASH_CFG_PROTO_1S_1S_1S;
Flash_norOspiSetProtocol
  Flash_set888mode
    Flash_norOspiRegRead(config, octCfg->cmdRegRd (0x85), octCfg->cfgReg (0), &reg (0xFF))
    Flash_norOspiRegWrite(config, octCfg->cmdRegWr (0x81), octCfg->cfgReg (0), reg (0xE7)); 
    OSPI_setProtocol((OSPI_Handle)(obj->ospiHandle), gFlashToSpiProtocolMap[pCfg->protocol]);
      OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x00033303	Device Read Instruction Configuration Register [Memory Mapped]	
      OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg	0x00033002	Device Write Instruction Configuration Register [Memory Mapped]	
      OSPI_enableDDR(handle)
        OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0x81783801	Octal-SPI Configuration Register [Memory Mapped]	
      OSPI_setDualOpCodeMode(handle)
        OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0xC1783801	Octal-SPI Configuration Register [Memory Mapped]	
      obj->protocol = protocol;
    obj->currentProtocol = pCfg->protocol;
  OSPI_setProtocol((OSPI_Handle)ospiHandle, gFlashToSpiProtocolMap[protocol]);
obj->currentProtocol = config->devConfig->protocolCfg.protocol;
Flash_norOspiSetAddressBytes(config, obj->ospiHandle)
  Flash_norOspiSet4ByteAddrMode
    Flash_norOspiCmdWrite(config, devCfg->cmdWren(0x06), OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
    Flash_norOspiCmdWrite(config, 0xB7, OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
  obj->numAddrBytes = 4;
  OSPI_setNumAddrBytes(ospiHandle, 4);
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg	0x00111003	Device Size Configuration Register [Memory Mapped]	
    obj->numAddrBytes = numAddrBytes;
OSPI_setXferOpCodes(obj->ospiHandle, config->devConfig->protocolCfg.cmdRd, config->devConfig->protocolCfg.cmdWr);
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x000333FD	Device Read Instruction Configuration Register [Memory Mapped]	
  OSPI_getCmdExt
    case OSPI_CMD_EXT_TYPE_INVERSE:
                cmdExt = ~cmd;
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg	0x0202FA7A	Opcode Extension Register (Lower) [Memory Mapped]	
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg	0x00033012	Device Write Instruction Configuration Register [Memory Mapped]	
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg	0x02EDFA7A	Opcode Extension Register (Lower) [Memory Mapped]	
Flash_norOspiSetModeDummy(config, obj->ospiHandle)
  OSPI_setReadDummyCycles(ospiHandle, pCfg->dummyClksRd)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg	0x100333FD	Device Read Instruction Configuration Register [Memory Mapped]	
    obj->rdDummyCycles = dummyCycles;
  OSPI_setCmdDummyCycles(ospiHandle, pCfg->dummyClksCmd)
    OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg	0x810A8400	Flash Command Control Register [Memory Mapped]	
    obj->cmdDummyCycles = dummyCycles;
  Flash_norOspiSetRegCfg(config, dCfg)
    Flash_norOspiRegRead(config, rCfg->cmdRegRd(0x85), rCfg->cfgReg(0x1), &cfgReg(0x1F))
    Flash_norOspiRegWrite(config, rCfg->cmdRegWr, rCfg->cfgReg, cfgReg(0x10))
OSPI_setRdDataCaptureDelay(obj->ospiHandle, readDataCapDelay)
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg	0x00000127	Read Data Capture Register [Memory Mapped]	
OSPI_phyReadAttackVector
  OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg	0xC1783881	Octal-SPI Configuration Register [Memory Mapped]

I also noticed that, when trying to do a CPU reset via ccs and load the image again after the call of the mentioned OSPI_phyReadAttackVector, the first read in SDR config won't work anymore and thus we can't read out the flash-id. We do - independently of the driver - have the same sequence you use in your driver-example:

    OSPI_norFlashSetCmds(0x03, 0x02, 0xD8);

    /* Initialize the flash device in 1s1s1s mode */
    OSPI_norFlashInit1s1s1s(ospiObject_.handle);
    /* Read ID */
    status = OSPI_norFlashReadId(ospiObject_.handle, &manfId, &deviceId);

This always worked with the old driver. With the new driver we need a power reset of the device to get this working. Else the read stuff is not correct. I guess the driver configures something different here but I don't know what.

Also some screenshots of how the read out memory looks after the call of OSPI_phyReadAttackVector at 0x60000000 via memory browser:

old driver:

it seems only some values match and then somehow all memory after that has the same value. Maybe that helps to identify the problem better.

Additionally here is our new configuration that I migrated:

#define FLASH_SIZE                  (32U * 1024U * 1024U)
#define FLASH_BLOCK_SIZE            (128U * 1024U)
#define FLASH_SECTOR_SIZE           (4U * 1024U)
#define FLASH_PAGE_SIZE             (256U)
#define FLASH_NUM_BLOCKS            (FLASH_SIZE / FLASH_BLOCK_SIZE)
#define FLASH_NUM_PAGES_PER_BLOCK   (FLASH_BLOCK_SIZE / FLASH_PAGE_SIZE)
#define FLASH_NUM_SECTORS           (FLASH_SIZE / FLASH_SECTOR_SIZE)

Flash_DevConfig gFlashDevCfg_IS25WX256T =
{
    .cmdExtType = OSPI_CMD_EXT_TYPE_INVERSE,
    .enable4BAddr = TRUE,
    .addrByteSupport = 1,
    .fourByteAddrEnSeq = 0x02, // NOR_CMD_4BEN
    .cmdWren = 0x06, // NOR_CMD_WREN
    .cmdRdsr = 0x05, // NOR_CMD_RDSR
    .srWip = (1 << 0), // NOR_SR_WIP
    .srWel = (1 << 1),
    .xspiWipRdCmd = 0x00,
    .xspiWipReg = 0x00000000,
    .xspiWipBit = (1 << 0),
    .resetType = 0x10, // NOR_CMD_RSTEN/NOR_CMD_RST_MEM
    .eraseCfg = {
        .blockSize = FLASH_BLOCK_SIZE,
        .sectorSize = FLASH_SECTOR_SIZE,
        .cmdBlockErase3B = 0xD8, // NOR_CMD_BLOCK_ERASE
        .cmdBlockErase4B = 0xDC, // NOR_CMD_BLOCK_ERASE
        .cmdSectorErase3B = 0x20, // NOR_CMD_SECTOR_ERASE
        .cmdSectorErase4B = 0x21, // NOR_CMD_SECTOR_ERASE
        .cmdChipErase = 0xC7, // NOR_CMD_BULK_ERASE
    },
    .idCfg = {
        .cmd = 0x9F, /* Constant */ // NOR_CMD_RDID
        .numBytes = 5, // NOR_RDID_NUM_BYTES
        .dummy4 = 0,
        .dummy8 = 0,
    },
    .protocolCfg = {
        .protocol = FLASH_CFG_PROTO_8D_8D_8D,
        .isDtr = TRUE,
        .cmdRd = 0xFD, // NOR_CMD_OCTAL_READ_DDR
        .cmdWr = 0x12, // NOR_CMD_PAGE_PROG
        .modeClksCmd = 0,
        .modeClksRd = 0,
        .dummyClksCmd = 8, // NOR_OCTAL_CMD_READ_DUMMY_CYCLE
        .dummyClksRd = 16, // NOR_OCTAL_READ_DUMMY_CYCLE
        .enableType = 0,
        .enableSeq = 0,
        .protoCfg = {
            .isAddrReg = TRUE,
            .cmdRegRd = 0x85, // NOR_CMD_RDCR2
            .cmdRegWr = 0x81, // NOR_CMD_WRCR2
            .cfgReg = 0x00000000, // NOR_DDR_EN_REG_ADDR
            .shift = 0,
            .mask = 0xFF,
            .cfgRegBitP = 0xE7, // NOR_DDR_EN_REG_DATA
        },
        .strDtrCfg = {
            .isAddrReg = TRUE,
            .cmdRegRd = 0x85, // NOR_CMD_RDCR2
            .cmdRegWr = 0x81, // NOR_CMD_WRCR2
            .cfgReg = 0x00000000, // NOR_DDR_EN_REG_ADDR
            .shift = 0,
            .mask = 0xFF,
            .cfgRegBitP = 0xE7, // NOR_DDR_EN_REG_DATA
        },
        .dummyCfg = {
            .isAddrReg = TRUE,
            .cmdRegRd = 0x85, // NOR_CMD_RDCR2
            .cmdRegWr = 0x81, // NOR_CMD_WRCR2
            .cfgReg = 0x00000001, // NOR_DUMMY_CYCLE_PROG_REG_ADDR
            .shift = 0,
            .mask = 0xFF,
            .cfgRegBitP = 16, // NOR_OCTAL_READ_DUMMY_CYCLE
        },
    },
    .flashWriteTimeout = 120, // NOR_PAGE_PROG_TIMEOUT
    .flashBusyTimeout = 256000000,
};

Flash_Attrs gFlashAttrs_IS25WX256 =
{
    .flashName = "IS25WX256",
    .deviceId = 0x5B19,
    .manufacturerId = 0x9D,
    .flashSize      = FLASH_SIZE,
    .blockCount     = FLASH_NUM_BLOCKS,
    .blockSize      = FLASH_BLOCK_SIZE,
    .pageCount      = FLASH_NUM_PAGES_PER_BLOCK,
    .pageSize       = FLASH_PAGE_SIZE,
    .sectorCount = FLASH_NUM_SECTORS,
    .sectorSize = FLASH_SECTOR_SIZE,
};

is there maybe another point inside the sdk that was changed that could have an impact here? But all other drivers are working fine. mcspi, pruicss, icssemac, clock, hwtimer, adc, gpios and so on are working as expected.

Also pls mention: I removed the subsequent Flash_norOspiReadId of the new driver, which was used to calculate the readDataCapDelay, since this never worked (it counted down to 0). I just set it hard to 3 which was the value of the old driver. But also this did not work.

The setting of the old driver were:

#include <board/flash.h>

Flash_NorOspiDevDefines gFlashNorOspiDeviceDefines_IS25WX256 = {

    .NOR_CMD_RSTEN                       = 0x66U,
    .NOR_CMD_RST_MEM                     = 0x99U,
    .NOR_CMD_WREN                        = 0x06U,
    .NOR_CMD_WRDI                        = 0x04U,
    .NOR_CMD_RDCR                        = 0x00U,
    .NOR_CMD_WRCR                        = 0x01U,
    .NOR_CMD_RDCR2                       = 0x85U,
    .NOR_CMD_RDCR2_NVO                   = 0xB5U,
    .NOR_CMD_WRCR2                       = 0x81U,
    .NOR_CMD_WRCR2_NVO                   = 0xB1U,
    .NOR_CMD_BULK_ERASE                  = 0xC7U,
    .NOR_CMD_BLOCK_ERASE                 = 0xDCU,
    .NOR_CMD_SECTOR_ERASE                = 0x21U,
    .NOR_CMD_RDSR                        = 0x05U,
    .NOR_CMD_RDID                        = 0x9FU,
    .NOR_CMD_RDSFDP                      = 0x5AU,
    .NOR_CMD_READ                        = 0x03U,
    .NOR_CMD_OCTAL_READ_SDR              = 0xCCU,
    .NOR_CMD_OCTAL_READ_DDR              = 0xFDU,
    .NOR_CMD_PAGE_PROG                   = 0x12U,
    .NOR_CMD_4BEN                        = 0xB7U,
    .NOR_SR_WIP                          = (1U << 0U),
    .NOR_RDID_NUM_BYTES                  = 0x5U,
    .NOR_MANF_ID                         = 0x9DU,
    .NOR_DEVICE_ID                       = 0x5B19U,
    .NOR_SINGLE_CMD_READ_DUMMY_CYCLE     = 0U,
    .NOR_OCTAL_CMD_READ_DUMMY_CYCLE      = 8U,
    .NOR_OCTAL_READ_DUMMY_CYCLE          = 16U,
    .NOR_OCTAL_READ_LC                   = 16U,
    .NOR_OCTAL_READ_DATA_CAP_DELAY       = 3U,
    .NOR_DDR_EN_REG_DATA                 = 0xE7U,
    .NOR_DDR_EN_REG_ADDR                 = 0x00000000U,
    .NOR_DUMMY_CYCLE_PROG_REG_ADDR       = 0x00000001U,
    .NOR_ADDRESS_CONFIG_REG_ADDR         = 0x00000005U,
    .NOR_WRR_WRITE_TIMEOUT               = 1200U,
    .NOR_BULK_ERASE_TIMEOUT              = 72000000,
    .NOR_PAGE_PROG_TIMEOUT               = 120U,
    .NOR_PAGE_SIZE                       = 256U,
};

#define FLASH_SIZE                  (32U * 1024U * 1024U)
#define FLASH_BLOCK_SIZE            (128U * 1024U)
#define FLASH_SECTOR_SIZE           (4U * 1024U)
#define FLASH_PAGE_SIZE             (256U)
#define FLASH_NUM_BLOCKS            (FLASH_SIZE / FLASH_BLOCK_SIZE)
#define FLASH_NUM_PAGES_PER_BLOCK   (FLASH_BLOCK_SIZE / FLASH_PAGE_SIZE)
#define FLASH_NUM_SECTORS           (FLASH_SIZE / FLASH_SECTOR_SIZE)

Flash_Attrs gFlashNorOspiAttrs_IS25WX256 = 
{
    .deviceId       = 0,  /* filled by Flash_open, after querying the flash */
    .manufacturerId = 0,  /* filled by Flash_open, after querying the flash */
    .driverInstance = 0,  /* filled by SysConfig */
    .flashSize      = FLASH_SIZE,
    .blockCount     = FLASH_NUM_BLOCKS,
    .blockSize      = FLASH_BLOCK_SIZE,
    .pageCount      = FLASH_NUM_PAGES_PER_BLOCK,
    .pageSize       = FLASH_PAGE_SIZE,
    .sectorSize     = FLASH_SECTOR_SIZE,
    .sectorCount    = FLASH_NUM_SECTORS,
};

We need the flash-driver to be working with the new sdk.

Best regards

Felix

over 2 years ago

0 Aakash Kedia over 2 years ago

TI__Mastermind 26025 points

Hi Felix Heil,

Thanks for this information and Apologies for inconvenience. This is everything I would have needed. Let me work through this and get back to you by 03/06/2023 ?

Best Regards,
Aakash

0 Aakash Kedia over 2 years ago in reply to Aakash Kedia

TI__Mastermind 26025 points

Hi Felix Heil,

I had a discussion with the expert and it was understood that the flash part supports only upto 1D-8D-8D which is not supported via syscfg. So I would recommend to use this function to bypass the syscfg -

And use the older flow of the driver in this function.

Hope it resolves your problem.

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash,

you mean the ISSI-Flash supports only 1D-8D-8D? Well we used it since with 8D-8D-8D and the data sheet as well guarantess an OCTAL-Mode-support with this setting up to 200 MHz.
But you mean I should then just drop the update? Or what do you mean with "older flow"?

Best regards,

Felix

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

Can you share the datasheet from which you found out that the device did support

Felix Heil said:
8D-8D-8D

Maybe that will help us understand the issue more. The datasheet we followed mentioned that only 1-8-8 is supported with this Flash.

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash,

the correct ident of the flash is IS25WX256. The datasheet says:

and

The datasheet should be available for free online.

Best regards,

Felix

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

Does this *.json configuration work for you ? I have done some modifications in the file shared.

/cfs-file/__key/communityserver-discussions-components-files/908/IS25WX256T.json

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash,

thanks for the Json. I tried to load is but an exception happens:

I tried it with SysCfg 1.14 and 1.15. Both run into this.

Best regards,

Felix

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix,

Please try the following fix -

1. So to fix these, firstly the correct copy command executable must be added i.e., "cp.exe" under the path C:\ti\<CCS_Version>\ccs\utils\cygwin to the environment variable as shown below, (confirm this by typing cp in the command line without any arguments and it should through an error "cp missing file operand")

2. Next step is to edit the flash_v0.syscfg.js file, in the line number 7 from "copy --> cp" as shown below

Now, save everything and try loading the JSON file in the sysconfig again.

Hope it helps.

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash, I tried the fix, now it loeads but then shows:

as the Flash name and no data is changed (still the default config)

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

Please check the updated file.

3364.IS25WX256T.json

{
    "flashSize": 33554432,
    "flashPageSize": 256,
    "flashManfId": "0x9D",
    "flashDeviceId": "0x5B19",
    "flashBlockSize": 131072,
    "flashSectorSize": 4096,
    "cmdBlockErase3B": "0xD8",
    "cmdBlockErase4B": "0xDC",
    "cmdSectorErase3B": "0x20",
    "cmdSectorErase4B": "0x21",
    "protos": {
        "p111": {
            "isDtr": false,
            "cmdRd": "0x03",
            "cmdWr": "0x02",
            "modeClksCmd": 0,
            "modeClksRd": 0,
            "dummyClksCmd": 0,
            "dummyClksRd": 0,
            "enableType": "0",
            "enableSeq": "0x00",
            "dummyCfg": null,
            "protoCfg": null,
            "strDtrCfg": null
        },
        "p112": null,
        "p114": null,
        "p118": null,
        "p444s": null,
        "p444d": null,
        "p888s": null,
        "p888d": {
            "isDtr": true,
            "cmdRd": "0xFD",
            "cmdWr": "0x12",
            "modeClksCmd": 0,
            "modeClksRd": 0,
            "dummyClksCmd": 8,
            "dummyClksRd": 16,
            "enableType": "0",
            "enableSeq": "0x00",
            "dummyCfg": {
                "isAddrReg": true,
                "cmdRegRd": "0x85",
                "cmdRegWr": "0x81",
                "cfgReg": "0x00000001",
                "shift": 0,
                "mask": "0xFF",
                "bitP": 16
            },
            "protoCfg": {
                "isAddrReg": true,
                "cmdRegRd": "0x85",
                "cmdRegWr": "0x81",
                "cfgReg": "0x00000000",
                "shift": 0,
                "mask": "0xFF",
                "bitP": 231
            },
            "strDtrCfg": {
                "isAddrReg": false,
                "cmdRegRd": "0x85",
                "cmdRegWr": "0x81",
                "cfgReg": "0x00000000",
                "shift": 0,
                "mask": "0xFF",
                "bitP": 231
            }
        },
        "pCustom": {
            "fxn": null
        }
    },
    "addrByteSupport": "1",
    "fourByteAddrEnSeq": "0x02",
    "cmdExtType": "REPEAT",
    "resetType": "0x10",
    "deviceBusyType": "1",
    "cmdWren": "0x06",
    "cmdRdsr": "0x05",
    "srWip": 0,
    "srWel": 2,
    "cmdChipErase": "0xC7",
    "rdIdSettings": {
        "cmd": "0x9F",
        "numBytes": 5,
        "dummy4": 0,
        "dummy8": 0
    },
    "xspiWipRdCmd": "0x00",
    "xspiWipReg": "0xFFFFFFFF",
    "xspiWipBit": 0,
    "flashDeviceBusyTimeout": 72000000,
    "flashPageProgTimeout": 120
}

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash,

I tried loading it, and it worked so far, but the values don't seem to be taken correctly:

Right is the one you just sent me, left is what SysCfg changed and did not change. Is this the correct behaviour?

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

I agree this is a valid issue which is reproducible on my end too. Can you enter the data manually for the fields not updated correctly via syscfg ? Also raised an internal ticket for the same.

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

hey Aaakash, ok.

But I may need a bit help here:

Where do I add the p111-setting?is this the "normal" protocolCfg-Field?

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

Felix Heil said:
Where do I add the p111-setting?is this the "normal" protocolCfg-Field?

I am sending out an example.syscfg which will configure the changes in the flash. Can you use those changes and try it on your setup ?

/cfs-file/__key/communityserver-discussions-components-files/908/2783.example.syscfg

Hope these changes help you.

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash,

so I tried the setting it with the values of the file you gave me ( I also needed to change the sdk-verswion inside the file to 08.05 to be able to open it in SysCfg) but unfortunately now it hangs here:

It can't escape this while-loop:

Best regards,
Felix

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

This debug is getting complicated and will result in more to and fros. Can we have a debug call for the same on Friday ? I can pull in more experts for the same.

Also at this step can you also share the Register Dump of OSPI CONFIG registers dump from 0xFC40000 to 0xFC400FC and also the dump of Memory Map i.e. 0x60000000 (1KB would be fine). Please share the same in TIDATA format for easier debug.

BR,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hey Aakash, this friday will not work.

Do you have a date for next week?

I will provide the mentioned dumps tomorrow.

Best regards,

Felix

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix,

Let's do it on Tuesday next week ?

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

On Tuesday i have some free time windows. I will write you a mail.

a dump of the flash only gives me this:

and OSPI-regs:

521177 13
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg 0x0000000B 0x80783801
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg 0x0000000B 0x00000003
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg 0x0000000B 0x00000002
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg 0x0000000B 0x0A0A0A0A
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg 0x0000000B 0x00000121
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg 0x0000000B 0x00111002
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg 0x0000000B 0x0000003F
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg 0x0000000B 0x00000001
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg 0x0000000B 0x00000001
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg 0x0000000B 0x000340FF
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg 0x0000000B 0xFFFFFFFF
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg 0x0000000B 0x00000010
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg 0x0000000B 0x01C02400
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg 0x0000000B 0x00000006
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg 0x0000000B 0x0000000F
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg 0x0000000B 0x05900000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg 0x0000000B 0x0000FFFF
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg 0x0000000B 0x000000E7
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg 0x0000000B 0x002E002B
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg 0x0000000B 0x00000010
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg 0x0000000B 0x9249BEFD
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg 0x0000000B 0x00160015
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg 0x0000000B 0x0302FA7A
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg 0x0000000B 0x06F90000
R FSS0_OSPI_0_OSPI0_CTRL_OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg 0x0000000B 0x03000300
R FSS0_OSPI_0_OSPI0_SS_CFG_OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID 0x0000000B 0x68747900
R FSS0_OSPI_0_OSPI0_SS_CFG_OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL 0x0000000B 0x00000000
R FSS0_OSPI_0_OSPI0_SS_CFG_OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT 0x0000000B 0x00000002
R FSS0_OSPI_0_OSPI0_SS_CFG_OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI 0x0000000B 0x00000000

or as memory dump directly:

ospi_reg_dump.dat

0 Aakash Kedia over 2 years ago in reply to Felix Heil

TI__Mastermind 26025 points

Hi Felix Heil,

As discussed in the call -

1. The sysconfig was not able to do the protocol writes hence, the suggestion is to comment out the Flash_norOspiSetProtocol and use the function in the attached file.

flash_protocol_issi.c

int32_t Flash_norOspiSet8D_ISSI(Flash_Config *config)
{
	Flash_NorOspiObject *obj = (Flash_NorOspiObject *)(config->object);
	uint8_t regData = 0xFF;
	int32_t status = SystemP_FAILURE;

    status = Flash_norOspiCmdWrite(config, 0x06, OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
	if (status == SystemP_SUCCESS)
	{
        /* Write 0xE7 to enable octal DDR */
        regData = 0xE7;
		status = Flash_norOspiCmdWrite(config, 0x81, 0x00, 3, &regData, 1);
	}
	
    /* Enable octal DDR in controller */
	OSPI_setProtocol((OSPI_Handle)(obj->ospiHandle), OSPI_NOR_PROTOCOL(8,8,8,1));

    /* Read back the register to check if the value is written correctly */
    uint8_t rxBuf[2] = { 0, 0};
    status = Flash_norOspiCmdRead(config, 0x85, 0x00, 3, 8, rxBuf, 2);
	
    /* Enable 4 byte address */
    status = Flash_norOspiCmdWrite(config, 0x06, OSPI_CMD_INVALID_ADDR, 0, NULL, 0);
    if (status == SystemP_SUCCESS)
    {
	    regData = 0xFE;
        status = Flash_norOspiCmdWrite(config, 0x81, 0x05, 3, &regData, 1);
    }
}

2. Also the dummy cycles was not being written for this flash due to

Skip this part of code as somehow ISSI flash is only able to read 1byte of data

Best Regards,
Aakash

0 Felix Heil over 2 years ago in reply to Aakash Kedia

Expert 1150 points

Hello Aakash,

Yes this is one part of the solution.

I noticed that this alone won't fix it. The data which was read was somehow looking correct but in fact was not.

The data I read after our debug-session was:

correct data will look like this:

I needed to change a bit more. I followed the old working driver and here I saw that the address-byte-number was changed to 4 before setting to OCTAL-SPI. The new driver maybe get confused because it sets the address-byte-number after OSPI-Part is being set to OCTAL-SPI. But as I understood at least the ISSI can only talk with 4-Byte-Address in OCTAL-SPI. So calling a command of address-byte setting after the OCTAL-SPI was configured with the previous 3-byte-address-setting, this would probably not work.
So I did it like this:

Which means my Flash_norOspiSet8D_ISSI only reaches until line 16 of your post, the rest is done before.

Also I noticed that the wait-ready function which was working in the old driver had some different settings so I tried it like it was before (else if):

But noticed that it doesn't matter if or if not the else if is taken. Behaviour seems to be the same.

Also the reg-read patch was done like this currently:

which works so far as well.

Also I changed the extCmd from REPEAT to INVERSE since this was the setting for the old driver.

I came to this point when setting the dummycycles (OSPI already configured to OCTAL). Right before OSPI_setReadDummyCycles data was wrong. right after OSPI_setReadDummyCycles data is correct:

from here on I checked the next functions. The Flash_norOspiSetRegCfg is called. Inside the patched Flash_norOspiRegRead is done which only reads 1 Byte. Data looks like this, but I guess that's ok in this case since the cmd-read was triggered? 1F is at least the value expected from the ISSI-register

Then the Flash_norOspiRegWrite is called. It works as far as I get into the wait-ready:

were you can see the data is there, but repeated.

But I think that's ok, since the dummycycles are not yet written. after calling the following Flash_norOspiCmdWrite-function, and before calling the next WaitReady it looks like this:

after calling:

And there I am currently. So it seems that in-between, when the dummy-cycles are set in OSPI the data seems to be read correct but somehow it gets wrong after configuring the ISSI to 16 dummycycles.
The WaitReady can be as patched like the old driver or not changed like in the new driver. the behaviour is not changed by that.

maybe this helps a bit more to identify the problem.

I really liked the good teamwork and progression last debug-session so if you want we can start another session again.

Best regards

Felix

Arm-based microcontrollers

Arm-based microcontrollers forum

MCU-PLUS-SDK-AM243X: SDK 08.05/08.04 new Flash-Driver not functional with ISSI Flash