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[FAQ] TMS570LC4357-EP: What is meant by this reference to "1024 Off-Chip Channels"?

Johnny Wyatt
Prodigy 10 points
Part Number: TMS570LC4357-EP

The smnu563a (Tech Ref Manual) refers to "1024 Off-Chip Channels" for ADC.

I don't see any other references for this. Is this just referring to handling SPI/I2C based external ADC chips, or is there some additional capability that this microcontroller has to integrate more tightly with external ADCs?

  • +1
    TI__Guru 55500 points

    Hi Johnny,

    Johnny Wyatt said:
    I don't see any other references for this. Is this just referring to handling SPI/I2C based external ADC chips, or is there some additional capability that this microcontroller has to integrate more tightly with external ADCs?

    There is a mode called "Enhanced Channel Selection Mode", using this mode we can extend analog channels upto 1024 channels.

    I will explain how but for more details refer "22.2.2.2.2 Enhanced Channel Selection Mode" section in TRM.

    As we know ADC1 instance will support upto 32 channels named AD1IN[0] to the AD1IN[31], These are called internal channels. In Sequential channel selection mode (default mode) we can connect 32 analog channels to these pins but in Enhanced channel selection mode we can extend these channels to upto 1024 by using external channel selection pins named: AD1EXT_SEL[4:0]

    Actually we can connect these external channel selection lines to the external multiplexers to extend the external channels in enhanced channel selection mode, like as below

    If you verify above diagram, ADC1 is the ADC instance-1 present in the controller, and as we know it have 32 input channels so what i am doing is, i connected one 32*1 mux to each input channel of the ADC1 instance.

    And this each 32*1 mux requires 5 selections right, so i am operating this selection lines with the AD1EXT_SEL[4:0]. 

    Actually in total we would have a 10 selection lines in ADC,  among them 5 are internal channel selection lines(AD1INT_SEL[4:0]) and 5 are external channel selection lines(AD1EXT_SEL[4:0]). This internal channel selection lines are automatically controlled by the EV_INT_CHN_MUX_SEL bits and external channel selection lines are controlled by the EV_EXT_CHN_MUX_SEL in enhanced channel selection mode.

    The channel selection table is listed in below image, please refer it.

    Now for more details of operation refer the "22.2.2.2.2 Enhanced Channel Selection Mode" section in TRM.

    --

    Thanks & regards,
    Jagadish.