AM243x is a System on Chip with a support of external flash. Customers are free to choose their custom flash. There are real challenges while integrating a custom flash. This FAQ will cover the problems faced during the SW configuration with AM243x device which has an xSPI controller.
Note: AM243x supports different flashes for different die.
It is assumed that the user already tried the Flash Integration via the steps mentioned here - https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/CUSTOM_FLASH_SUPPORT_GUIDE.html
This FAQ walks you through the integration of MX25U51245GXDI00 (Macronix flash) which is not part of TI's EVM to emulate an experience of Custom Flash Integration.
1s-1s-1s mode is the simplest step one should start with. It has least amount of variables that impact the flash functioning.
Fill the following items in the syscfg of the ospi_io example
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Configurable Items
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|---|
| Block Erase CMD (3B) |
| Block Erase CMD (4B) |
| Chip Erase Command |
| Flash Block Size In Bytes |
| Flash Busy Timeout |
| Flash JEDEC Device ID |
| Flash JEDEC Manufacturer ID |
| Flash Page Size In Bytes |
| Flash Sector Size In Bytes |
| Flash Size In Bytes |
| Page Program Timeout |
| Read Status Register CMD |
| Sector Erase CMD (3B) |
| Sector Erase CMD (4B) |
| WEL Bit |
| WIP Bit |
| Write Enable CMD |
| Write/Page Program Command |
Rebuild the Test Application of OSPI IO with these changes. Make sure to keep the BOOT MODE as DEV-BOOT MODE for these type of tests. If this does not work recheck the configurations with the datasheet or SFDP table. If every thing is OK with the SW, recheck the HW.
These changes are in difference with the Previous step and in assumption that the previous steps have worked for 1s-1s-1s standard read.
Note that the Configuration is only supported to write 1B(8bit) register only. If data to be written is > 8bits, this requires changes in the Flash Driver.
For MX25U51245GXDI00, the Write register writes 2B at a time, so this requires re-writing the driver to support the same like this (function name Flash_norOspiSetRegCfg)
Rebuild the Test Application of OSPI IO with these changes. Make sure to keep the BOOT MODE as DEV-BOOT MODE for these type of tests. If this does not work recheck the configurations with the datasheet or SFDP table.
Details on QE bit as given in the syscfg information (?) -
Rebuild the Application Test the application of OSPI_IO with these changes. If this does not work recheck the configurations with the datasheet or SFDP table. If every thing is OK with the SW, recheck the HW.
Details on QPI Sequence as given in the syscfg information (?)
Rebuild the Test Application of OSPI_IO with these changes. If this does not work recheck the configurations with the datasheet or SFDP table.
Rebuild the Test Application of OSPI_IO with these changes. If this does not work recheck the configurations with the datasheet or SFDP table.
This is the maximum configuration supported by this Flash but here are some tips for higher configurations
To be done After 1s-1s-4s mode.
Details on Octal Enable Bit as given in the syscfg information (?)
To be done After 1s-1s-8s mode.
Details on OPI Sequence as given in the syscfg information (?)
To be done After 4s-4s-4d mode.
Details on Octal Enable Bit as given in the syscfg information (?)
Details on OPI Sequence as given in the syscfg information (?)
Q. When should PHY be enabled ?
A. PHY should not be enabled till the operating frequency for DTR <= 25MHz and STR <= 50MHz. Also the PHY configuration provided by SDK is only optimum for 8d-8d-8d (for Cypress Flash on the EVM), hence is suggested to kept disabled.
Q. What if the protocol, user needs to run is not part of SYSCFG ?
A. This needs the driver to be re-written by the user as this protocol is not a standard protocol. However, it might be supported by the Hardware, SDK might not support it out of the box due to its complexity and specific implementation.
Q. What is the maximum frequency supported by the Hardware ?
A. With PHY enabled, the maximum frequency supported is 200MHz. However it is suggested to keep the operating frequency as 133MHz to sustain at all PVT values.
Q. How to configure the divider if the PHY is enabled ?
A. When the PHY is enabled, the divider values are ignored.
Q. What if the read values are not matching with the ones written ?
A. Check the Dummy Cycles values. Sometimes the dummy cycle values may be a little bit different from the one mentioned in the datasheet. Also if there is still data misalignment then user might have to call OSPI_setRdDataCaptureDelay API after the Flash_open().
