hi,
I am using the PMU to count data cache miss rates. The numbers I am getting dont seem plausible as the number of data cache misses (DCache Miss Count) is greater than the number of cache accesses(DCache Access Count). I looked up the following example on the TI and there I see the same:
Thanks and best regards,
Ali Arshad
Hi Ali,
I will do a quick test on AM263x device using AM26x SDK. I did performance measurement on TMS570 before, and the cache access count is always bigger than the cache miss count:
I wrote a note of using PMU on TMS570 device:
Hi Ali,
I reviewed the source code of PMU driver. I think there is a bug in PMU counter setting. The line #143 and line #144 should be deleted, otherwise, the event counter 3 (used for dcache miss) is to count the CPU cycles. I will file a bug ticket tomorrow.
