AM2634: Loading program via XDS110 fails

Hello Saman,

Saman Mardani said:

and how about the boot modes? must it be in "No boot" mode? 

For programming with JTAG yes you would need to be in NO BOOT mode. Is this what has been selected?

Saman Mardani said:

Is there any change that I should made in AM2631.ccxml?

Unlikely, at least not the first thing we should attempt here.

Saman Mardani said:

I have designed my own board based on AM2634 MCU and try to connect and load the program via XDS110.

For starters here, have you been able to program the board successfully with any other modes? Do you have support for UART implemented? If not, I would say the first step with a new board is to make sure you have all the power sequencing properly addressed and that the MCU is able to boot properly.

Here are three areas I'd like to you to verify and provide details on:

• Power Supply Sequencing
• PORz release timing
• Clock stability

Best Regards,

Ralph Jacobi

Hi Ralph,

Thank you for the reply

Ralph Jacobi said:

For starters here, have you been able to program the board successfully with any other modes?

Unfortunately not yet.

Ralph Jacobi said:

Do you have support for UART implemented?

Yes, but it is connected to the Auxiliary connector of XDS110 which is not connected now. I can connect it later.

Ralph Jacobi said:

make sure you have all the power sequencing properly addressed and that the MCU is able to boot properly.

Can you send the guideline for this?

Ralph Jacobi said:

Here are three areas I'd like to you to verify and provide details on:

• Power Supply Sequencing
• PORz release timing
• Clock stability

I will check the "Power Supply Sequencing" today and come back to you. Although all MCU voltages 3.3V and 1.2V and 1.8 are checked and valid.

PORz release timing also seems to be fine. I will send oscilloscope shot later to you.

XTALs are oscillating at 25Mhz frequency. is there anything more that I should check for clock stability?

Best Regards

Saman

Hello Saman,

Saman Mardani said:

Can you send the guideline for this?

For Sequencing, please refer to Section 7.11.2 Power Supply Sequencing of the Device Datasheet.

Saman Mardani said:

PORz release timing also seems to be fine. I will send oscilloscope shot later to you.

A scope shot will be helpful, thanks.

Saman Mardani said:

XTALs are oscillating at 25Mhz frequency. is there anything more that I should check for clock stability?

That's good, only other consideration would be to verify the load capacitance is within range of specifications for crystal and MCU.

Best Regards,

Ralph Jacobi

Hi Ralph,

Here is the scope shot of the PORz and MCU input supply

and Here is the scope shot of the XTAL_XI input pin of the MCU. As I have indicated the max/min voltage levels are 1.32V and 380mV and the frequency is 25 Mhz.

Is that fine?

Still "Connection verification" is working well 

But when Loading program, I get this error.

Would you please kindly tell me what exactly this error means? and how to resolve it?

By the way, SOP0-3 are in NoBoot Mode "1101"

BR

Saman

Hi Erik,

Thank for the reply,

Erik Friedel said:

If you open the CCXML and click on the Target Configuration link, does the R5_0 point to the AM263x.gel?

         Yes, It points to AM263x.gel

Erik Friedel said:

Did you alter the initialization gel script?

No, I have not changed it. I try to load "Hello World" Example from SDK without any changes.

Erik Friedel said:

Did you alter anything within sysconfig that may have changed some clock frequencies? 

No. Hello world example without any changes.

Erik Friedel said:

This is the correct but to confirm, are you referring to the following

Yes, Exactly 

• SOP0: QSPI_D0  : 1
• SOP1: QSPI_D1  : 1
• SOP2: SPI0_CLK : 0
• SOP3: SPI0_D0   : 1

By the way, the following report is generated before getting the FOUT != 0 error,

Cortex_R5_0: GEL Output: Loading Gel Files on R5F0
Cortex_R5_0: GEL Output: Gel files loading on R5F0 Complete
Cortex_R5_0: GEL Output: ***OnTargetConnect() Launched***

Cortex_R5_0: GEL Output: AM263x Initialization Scripts Launched.
Please Wait...

Cortex_R5_0: GEL Output: AM263x_Cryst_Clock_Loss_Status() Launched
Cortex_R5_0: GEL Output: Crystal Clock present
Cortex_R5_0: GEL Output: AM263x_SOP_Mode() Launched
Cortex_R5_0: GEL Output: SOP MODE = 0x0000000D
Cortex_R5_0: GEL Output:
ERR... Reserved boot mode
Cortex_R5_0: GEL Output: AM263x_Read_Device_Type() Launched
Cortex_R5_0: GEL Output: EFuse Device Type Value = 0x000000AA
Cortex_R5_0: GEL Output: AM263x_Check_supported_mode() Launched
Cortex_R5_0: GEL Output:
efuse1=0x01000000
Cortex_R5_0: GEL Output:
The Device supports both LockStep & Dual Core mode
Cortex_R5_0: GEL Output:
mode = 0
Cortex_R5_0: GEL Output: MSS_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_TOP_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_RCM Control Registers Unlocked
Cortex_R5_0: GEL Output: MSS_IOMUX Control Registers Unlocked
Cortex_R5_0: GEL Output: TOP_CTRL Control Registers Unlocked
Cortex_R5_0: GEL Output:

***R5FSS0 Reset for Lockstep ***
Cortex_R5_0: GEL Output:

*** R5FSS1 Reset for Lockstep ***
Cortex_R5_0: GEL Output: R5F ROM Eclipse
Cortex_R5_0: GEL Output: R5FSS0_0 Released
Cortex_R5_0: GEL Output: R5FSS0_1 Released
Cortex_R5_0: GEL Output: R5FSS1_0 Released
Cortex_R5_0: GEL Output: R5FSS1_1 Released
Cortex_R5_0: GEL Output:

All R5F Cores Released for program load
Cortex_R5_0: GEL Output: L2 Mem Init Complete
Cortex_R5_0: GEL Output: MailBox Mem Init Complete
Cortex_R5_0: GEL Output: *********** R5FSS0/1 Lockstep mode Configured********
Cortex_R5_0: GEL Output: PER PLL Configuration Complete
Cortex_R5_0: GEL Output: SYS_CLK DIVBY2
Cortex_R5_0: GEL Output: DPLL_CORE_HSDIV0_CLKOUT0 selected as CLK source for R5FSS & SYS CLKs
Cortex_R5_0: GEL Output:
CLK Programmed R5F=400MHz and SYS_CLK=200MHz
Cortex_R5_0: GEL Output:

*** Enabling Peripheral Clocks ***
Cortex_R5_0: GEL Output: Enabling RTI[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling RTI_WDT[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling UART[0:5]/LIN[0:5] Clocks
Cortex_R5_0: GEL Output: Enabling QSPI Clocks
Cortex_R5_0: GEL Output: Enabling I2C Clocks
Cortex_R5_0: GEL Output: Enabling TRACE Clocks
Cortex_R5_0: GEL Output: Enabling MCAN[0:3] Clocks
Cortex_R5_0: GEL Output: Enabling GPMC Clocks
Cortex_R5_0: GEL Output: Enabling ELM Clocks
Cortex_R5_0: GEL Output: Enabling MMCSD Clocks
Cortex_R5_0: GEL Output: Enabling MCSPI[0:4] Clocks
Cortex_R5_0: GEL Output: Enabling CONTROLSS Clocks
Cortex_R5_0: GEL Output: Enabling CPTS Clocks
Cortex_R5_0: GEL Output: Enabling RGMI[5,50,250] Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_TEMPSENSE_32K Clocks
Cortex_R5_0: GEL Output: Enabling XTAL_MMC_32K Clocks
Cortex_R5_0: GEL Output:

***All IP Clocks are Enabled***

Cortex_R5_0: GEL Output: CPU reset (soft reset) has been issued through GEL.

Best Regards

Saman

Hi Erik,

The problem is resolved now.

Boot Mode was not correctly set as I expected.

BR

Saman