• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 31 subscribers
  • Views 447 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM2434: Recommended Typ PCB single-ended impedance and differential impedance for DDR and PCIE

AM2434: Question about AM2434 PCIE

Jayden Qiu
Intellectual 1145 points
Part Number: AM2434

Hi Team,

This is FAE Jayden, my customer o-net is evaluating AM2434 in their projects. Here is one question they raised. Could you help support?

When PCIE was communicating normally in GEN2 mode, it was changed to the working mode of GEN1 (the working environment and code were the same, so only the working mode was changed), and it was found that it could not communicate normally. The debugging screenshot is as follows:

New Microsoft PowerPoint Presentation.pptx

Brs

Jayden

  • 0
    TI__Intellectual 2695 points

    Hi Jayden,

    I am not clear on the question. Did the customer change the example syscfg for both pcie legacy irq ep/rc modes to Gen1 mode and the example did not work for Gen1 mode?

    Thank you,

    Anita

  • 0 in reply to Anita Pratti
    TI__Expert 3165 points

    Hi Anita,

    Could you have a try or verify pcie legacy irq ep/rc example whether work for Gen1 mode? Thanks.

  • 0 in reply to Shaoxing Ke
    TI__Intellectual 2695 points

    Hello Shaoxing,

    I am following up on this and will get back to you in a couple of days.

    Thank you,

    Anita

  • 0 in reply to Anita Pratti
    TI__Intellectual 1145 points

    Hi  Anita,

    Thanks for your support.AM2434 has a good reputation in O-NET and this issue is the key barrier in their project development. So could you help accelerate  the verify progress? Thanks.

    Brs

    Jayden

  • 0 in reply to Jayden Qiu
    TI__Intellectual 2695 points

    Hi Jayden, Shaoxing,

    I am following up internally on this and will get back to you as soon as I get any feedback.

    Thank you,

    Anita

  • +1 in reply to Anita Pratti
    Mastermind 6605 points

    Hi,

    the driver in the current MCU+ SDK fails to actually restrict the PCIe linkcapabilities and uses this setting only to verify if a link with the desired parameters has been established.

    I guess what your customer actually wants is to artifically limit the connection so that only a Gen1 link can be established?

    You could have them modify the EP example code to include the following lines BEFORE the call to Drivers_open:

        extern Pcie_DevParams Pcie_devParamsDev1;
    Pcie_devParamsDev1.linkSpeed = 1;

    With that change the EP should modify its capability bits to indicate support for 2.5GT/s ("Gen1") only.

    To ensure the change has the desired effect they could monitor the content of registers 0x0d0000cc (PCIE0_RC_i_rc_pcie_base_i_link_cap) and 0x0d0000ec (PCIE0_RC_i_rc_pcie_base_i_link_cap_2). If the PCIe core is configured to support both Gen1 and Gen2, these registers read 0x41a812 (link_cap) and 0x30606 (link_cap2). If the core is configured to support only Gen1 speeds, these registers read 0x41a811 (link_cap) and 0x10202 (link_cap2). Those registers can't be configured directly from the EP, but the GENERATION_SEL field in CTRLMMR_PCIE0_CTRL determines these bits, and the PCIe driver sets that field based on Pcie_devParamsDev1.linkSpeed.

    Regards,

    Dominic