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FIQ Handling Prior to VIM initialization

Lucas Wendling
Prodigy 150 points

I'm running into an issue I don't fully understand.  I have an FIQ occuring at initialization on the TMS570 prior to setting up the VIM and prior to enabling FIQs via the CPSR register.  In this case it is an ESMH error, which for the 570 is setup as an NMI on VIM channel 0.  The following are what I think are the relevant steps in my startup sequence:

1) Power On:

ESMH error is active.  FIQIVec register is set to "1" which properly indicates channel 0 (ESMH) interrupt.  However, since the VIM has not yet gone though initialization, FiqVecReg doesn't have the proper address for ESMH interrupt handler routine.  "F" bit in CPSR is "1" - FIQs disabled.

2)  VIM Initialization occurs:

VIM is initialized for priority mapping and the interrupt vector tables are populated by coping proper addresses into VIM RAM. "F" bit in CPSR is still "1" - FIQs disabled. However, I am noticing that as the copy is occurring to populate the interrupt vector tables, the IrqVecReg and the FiqVecReg are both getting set to the address of the phantom interrupt vector.

3) FIQ interrupts get enabled:

Some time later, I clear the "F" bit in CPSR to enable FIQs.  This then causes the pending FIQ that occured at power on to be serviced.  My FIQ interrupt handler jumps to the address in FIQVecReg, which is incorrectly pointing to the phantom interrupt vector (Ideally it would be pointing to my ESMH interrupt handler).

I think this leads me to two questions:  What is the recommend method for handling ISR requests prior to the VIM being configured (or at least some suggestions)?  Also, what would be causing the IrqVecReg and FiqVecReg to be populated with the phantom interrupt vector when VIM RAM is being loaded in step 2?

  • 0
    TI__Genius 13810 points

    1. The VIM logic probes the first write to the Phantom address in the VIM_RAM and update the IrqVecReg and FiqVecReg registers with this new write address.

    2. We are going to publish a initialization application note next week. My opinion is: There should not be any interupt occurring before the VIM is initilized. If you use a TMS570LS20x series, please start your code with sth like the following to avoid core compare errors:

    mov r0, lr

    mov r1, #0x0000

    mov r2, #0x0000

    mov r3, #0x0000

    mov r4, #0x0000

    mov r5, #0x0000

    mov r6, #0x0000

    mov r7, #0x0000

    mov r8, #0x0000

    mov r9, #0x0000

    mov r10, #0x0000

    mov r11, #0x0000

    mov r12, #0x0000

  • 0 in reply to Haixiao Weng
    Genius 5660 points

    Hello Haixiao,

    You said

    " The VIM logic probes the first write to the Phantom address in the VIM_RAM and update the IrqVecReg and FiqVecReg registers with this new write address."

    Does this mean before writing to VIM RAM or enabling CPSR F Bit, one must clear all pending ESM Errors?

    Can you please elaborate somewhat more about your FIRST statement?

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Genius 13810 points

    Pashan None said:

    Hello Haixiao,

    You said

    " The VIM logic probes the first write to the Phantom address in the VIM_RAM and update the IrqVecReg and FiqVecReg registers with this new write address."

    HW: During startup, the application will initilize the VIM RAM. The offset address 0 is the Phantom ISR. After reset, when this address is written (only for the 1st time after the reset), the IrqVecReg and FigVecReg will be modified to this Phantom ISR.

    Suppose an ESM Error occurs at the very beginning, the IrqVecRg and FigVecReg is updated once the error occurs. This is an ESM error. IrqVecRg and FigVecReg will be updated with the Phantom ISR when you initilized the VIM RAM. Once you enabled the CPSR I,Q bit, you will get a phantom interrupt. (It should be an ESM interrupt indeed).

    I prefer to check and procees and clear all the pending ESM Error before VIM RAM is initilized and CPSR I,Q are enabled.

    Does this mean before writing to VIM RAM or enabling CPSR F Bit, one must clear all pending ESM Errors?

    Can you please elaborate somewhat more about your FIRST statement?

    Thank you.

    Regards

    Pashan