AM2432: OSPI FLASH address of the out file

Hi Aakash,

I reopen our discussion for there are still some problems.

1. I've loaded the SDK CLANG "hello_world.hs_fs" with ftp to FLASH @ 0x80000  and it works,  but Bootloader_socAuthImage(0x80000); returnes -1 !

2. I've compiled my GCC version of Hello World .

I've loaded  "my_hello_world.hs_fs" with ftp FLASH @ 0x80000  and it works, but also Bootloader_socAuthImage(0x80000); returnes -1 !

Maybe I should not give the 0x80000 as parameter but something else ?

3. Now the more severe problem - I load my GCC app.hs_fs with ftp (which is ~3Mbytes ) 

when I toggle the power I get :

TR Response failed for transfer : SRC = 0x601FF300, DST = 0x21000014, SIZE = 2064384

ASSERT: 0.600316s: ospi/v0/dma/udma/ospi_dma_udma.c:OspiDma_udmaUpdateSubmitTR:242: FALSE failed !!!

How to proceed ?

Thanks,

Best Regards,

Eli

Hi Eli,

Eli Mordel said:

Maybe I should not give the 0x80000 as parameter but something else ?

The address passed to the `Bootloader_socAuthImage` is the SoC address of the signed appimage (.appimage.hs_fs).

AM243x MCU+ SDK: bootloader_soc.h File Reference (ti.com)

When requesting the authentication of an appimage in OSPI, the OSPI needs to be in DAC mode so that it is memory mapped to the FSS0_DAT_REG1 address space

FSS0_DAT_REG1   0x060000000     0x067FFFFFF     128 MB

Then, the corresponding SoC address for flash offset 0x80000 would be 0x60080000 which can be passed to `Bootloader_socAuthImage`.

Eli Mordel said:

TR Response failed for transfer : SRC = 0x601FF300, DST = 0x21000014, SIZE = 2064384

The destination address does not look right. Can you please share your application's linker map file?

Regards,

Prashant

Hi Prashant,

How do I put the OSPI in DAC mode , Is there a set of commands ?

Here is my linker code :

/*-include ti_enet_config.h*/
CONFIG_ENET_CPSW0 = 0;
ENET_SYSCFG_MAX_ENET_INSTANCES = 1;
ENET_SYSCFG_TOTAL_NUM_TX_PKT = 16;
ENET_SYSCFG_TOTAL_NUM_RX_PKT = 32;
ENET_SYSCFG_PKT_POOL_ENABLE = 1;
ENET_SYSCFG_PKT_INFO_ONLY_ENABLE = 1;
ENET_SYSCFG_MAX_MAC_PORTS = 1;
ENET_SYSCFG_ENABLE_EXTPHY = 0;
ENET_SYSCFG_ENABLE_MDIO_MANUALMODE = 1;
ENET_SYSCFG_RX_FLOWS_NUM = 1;
ENET_SYSCFG_TX_CHANNELS_NUM = 1;
ENET_SYSCFG_RING_MON_NUM = 3; /*Not appicable for LCDMA devices*/
ENET_DMA_TX_CH0 = 0;
/* RX DMA Channel indexes. Name of RX DMA channel can be changed in example syscfg */
/* Application should use the define below when opening a Rx DMA channel */
ENET_DMA_RX_CH0 = 0;
/* TX DMA max num packets allocated to the DMA channel */
/* Application should use the define below when opening a Tx DMA channel */
ENET_DMA_TX_CH0_NUM_PKTS = 16;
/* RX DMA DMA max num packets allocated to the DMA channel */
/* Application should use the define below when opening a Rx DMA channel */
ENET_DMA_RX_CH0_NUM_PKTS = 32;
/* NETIF indexes. Name of NETIF can be changed in example syscfg */
/* Application should use the define below when opening a NETIF */
NETIF_INST_ID0 = 0;
ENET_SYSCFG_NETIF_COUNT = 1;
ENET_SYSCFG_DEFAULT_NETIF_IDX = 0; /*eli was (NETIF_INST_ID0)*/
/*
* Packet sizes for different pools. LARGE_POOL is largest packet size pool with MEDIUM_POOL
* second largest and SMALL_POOL smallest
*/
/*eli found in sdk #define ENET_UTILS_ALIGN(x, y) ((((x) + ((y) - 1)) / (y)) * (y))*/
/*eli found in sdk #define ENETDMA_CACHELINE_ALIGNMENT (32U)*/
/*eli found in sdk #define ENET_UTILS_CACHELINE_SIZE (ENETDMA_CACHELINE_ALIGNMENT) */
/*#define ENET_MEM_LARGE_POOL_PKT_SIZE ENET_UTILS_ALIGN(1536U, ENET_UTILS_CACHELINE_SIZE)*/
/*#define ENET_MEM_MEDIUM_POOL_PKT_SIZE ENET_UTILS_ALIGN(512U, ENET_UTILS_CACHELINE_SIZE)*/
/*#define ENET_MEM_SMALL_POOL_PKT_SIZE ENET_UTILS_ALIGN(128U, ENET_UTILS_CACHELINE_SIZE)*/
ENET_MEM_LARGE_POOL_PKT_SIZE = 1567; /* ((((1536) + ((32) - 1)) / (32)) * (32)) */
ENET_MEM_MEDIUM_POOL_PKT_SIZE = 543; /* ((((512) + ((32) - 1)) / (32)) * (32)) */
ENET_MEM_SMALL_POOL_PKT_SIZE = 159; /* ((((128) + ((32) - 1)) / (32)) * (32)) */

/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
/*--stack_size=8192*/
__TI_STACK_SIZE = 10 * 32768; /*{!} eli was 8 * 32768;/*{!}eli was 4 * 32768 was 8192*/

/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/

/*--heap_size=34000*/
__TI_HEAP_SIZE = 1024 * 1024; /*was 4 * 1024*/

/*-e_vectors*/ /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
ENTRY(_vectors) /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */

/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is disabled as of now
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is enabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = 1024;/*256*/;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = 1024;/*256;*/
__SVC_STACK_SIZE = 8192;/*4096;*/ /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 1024;/*256;*/ /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 2048;/*1024;*//*256;*/ /* This is the size of stack when R5 is in UNDEF mode */

/*__STACK_END = 0x800B2C50;*/ /*eli was 0x80100000; eli was 0x80000;*/

MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000

/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x15FFFF /*eli changed not to colide with USER_SHM_MEM was : ORIGIN = 0x70080000 , LENGTH = 0x10000*/

/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x60200000 , LENGTH = 0x800000

/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
DDR : ORIGIN = 0x80000000 , LENGTH = 0x20000000 /*0x3F0000*/ /*{!}eli was LENGTH = 0x120000 */

/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00004000
LOG_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x00004000
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D8000, LENGTH = 0x00008000
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
}

SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
/*.vectors:{} palign(8) > R5F_VECS*/
.vectors : ALIGN (8) {} > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
.text.hwi : ALIGN (8) {} > MSRAM /*.text.hwi: palign(8)*/
.text.cache : ALIGN (8) {} > MSRAM /*.text.cache: palign(8)*/
.text.mpu : ALIGN (8) {} > MSRAM /*text.mpu: palign(8)*/
.text.boot : ALIGN (8) {} > MSRAM /*.text.boot: palign(8)*/
.text.startup : ALIGN (8) {} > MSRAM
.text.abort : ALIGN (8) {} > MSRAM /*.text:abort: palign(8)*/ /* this helps in loading symbols when using XIP mode */

.text : ALIGN (8) {} > DDR /*.text: {} palign(8)*/ /* This is where code resides */
.rodata : ALIGN (8) {} > DDR /*.rodata: {} palign(8)*/ /* This is where const's go */

.data : ALIGN (8) {} > DDR /*.data: {} palign(8)*/ /* This is where initialized globals and static go */

.freertos_data (NOLOAD) : ALIGN(8)
{

_s_freertos_data = .; /* Start address of the .freertos_data section */
*(.freertos_data)
_e_freertos_data = .; /* End address of the .freertos_data section */
} > DDR

.sysmem (NOLOAD) : ALIGN (8)
{
__TI_HEAP_START = .;
. = . + __TI_HEAP_SIZE;
__TI_HEAP_END = .;
} > DDR /*.sysmem: {} palign(8)*/ /* This is where the malloc heap goes */

/* .stack : ALIGN (8) {} > DDR */ /*.stack: {} palign(8)*/ /* This is where the main() stack goes */
.stack (NOLOAD) : ALIGN (8)
{
__TI_STACK_BASE = .;
__stack_start = .;
__stack = .;
/* Define the stack section here */
. = ALIGN(8);
. = . + __TI_STACK_SIZE;
. = ALIGN(8);
} > DDR

__STACK_END = .;

.bss : {
__bss_start__ = .;
*(.bss)
*(.bss.*)
. = ALIGN (8);
*(COMMON)
__bss_end__ = .;
. = ALIGN (8);
} > DDR

__BSS_START = __bss_start__;
__BSS_END = __bss_end__;

.irqstack : ALIGN (8) {__IRQ_STACK_START = .;
. = . + __IRQ_STACK_SIZE;
__IRQ_STACK_END = .;
} > DDR

.fiqstack :ALIGN (8){ __FIQ_STACK_START = .;
. = . + __FIQ_STACK_SIZE;
__FIQ_STACK_END = .;
} > DDR

.svcstack : ALIGN (8){__SVC_STACK_START = .;
. = . + __SVC_STACK_SIZE;
__SVC_STACK_END = .;
} > DDR

.abortstack : ALIGN (8) {__ABORT_STACK_START = .;
. = . + __ABORT_STACK_SIZE;
__ABORT_STACK_END = .;
} > DDR

.undefinedstack : ALIGN (8) {__UNDEFINED_STACK_START = .;
. = . + __UNDEFINED_STACK_SIZE;
__UNDEFINED_STACK_END = .;
} > DDR

/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM

.enet_dma_mem (NOLOAD) : ALIGN(128) {
*(*ENET_DMA_DESC_MEMPOOL)
*(*ENET_DMA_RING_MEMPOOL)
/*#if (ENET_SYSCFG_PKT_POOL_ENABLE==1)*/
*(*ENET_DMA_PKT_MEMPOOL)
/*#endif*/
} > DDR

.bss (NOLOAD) : ALIGN (128) {*(ENET_DMA_OBJ_MEM)} > DDR
.bss (NOLOAD) : ALIGN (128) {*(ENET_DMA_PKT_INFO_MEMPOOL)} > DDR
.bss (NOLOAD) : ALIGN (128) {*(ENET_ICSSG_OCMC_MEM)} > DDR

__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > DDR

__exidx_end = .;

.preinit_array : ALIGN(4)
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > DDR /*originally MSRAM_TEXT*/

.init_array : ALIGN(4)
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > DDR /*originally MSRAM_TEXT*/

.fini_array : ALIGN(4)
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > DDR /*originally MSRAM_TEXT*/

}/*SECTIONS*/

/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701FC000 - 0x701FFFFF (16KB)

Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER

This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/

Thanks,

Regards,

Eli

Hi Eli,

Eli Mordel said:

How do I put the OSPI in DAC mode , Is there a set of commands ?

There is an API available for this

AM243x MCU+ SDK: APIs for OSPI (ti.com)

Eli Mordel said:

Here is my linker code :

The memory regions looks all okay. Can you please share the generated map file (*.map) file?

Also, what is the SDK version you are using here?

And I assume the TR Response failed error comes from the SBL while trying to load application. Is this right?

Regards,

Prashant

Hi Prashant,

I'm using mcu_plus_sdk_am243x_08_06_00_43.

For smaller ~ 105k hs_fs files all work well !

I've noticed a very starage behaviour if I do Flash_write(..) then same address and size Flash_read(.. in a loop.

Should I use Flash_reset( in between ?

The map file is ~13Mbytes , Do you want me to attach all of it (zipped) ?

I can copy parts - which part is relevant for the investigation ?

Thanks,

Regards,

Eli

Hi Eli,

Eli Mordel said:

I've noticed a very starage behaviour if I do Flash_write(..) then same address and size Flash_read(.. in a loop.

Should I use Flash_reset( in between ?

What is the address & size here that causes the Flash_read to fail? There should be no need of Flash_reset. The ospi_flash_io example uses Flash_read directly after Flash_write.

Eli Mordel said:

The map file is ~13Mbytes , Do you want me to attach all of it (zipped) ?

You can attach of it. Zipping it would reduce the size significantly for attaching.

Regards,

Prashant

Hi Prashant,

I zipped it  now ~600KB , when I drag it to this window - it is not attached.

Why do I get TR Response failed for transfer : SRC = 0x601FF300, DST = 0x21000014, SIZE = 2064384 ?

What is TR ?

Why do you think the addresses are not correct ?

Thanks,

Regards,

Eli

Hi Prashant,

I've noticed another problem :When I write a lot of data to the flash I see value mismatches in many bytes - the flash is not properly burned .

Please advice.

Thanks,

Regards,

Eli

Hi Prashant,

Please ignore my last problem about flash mismatches in bytes - I've checked again and it is OK , sorry my mistake.

But the original problem is still occurs:

I write my.hs_fs file to flash address 0x80000 I check crc and compare to it to the pc file - exact crc and size !

When I reboot I get  Image loading done, switching to application ... but nothing happens 

Thanks,

Regards,

Eli

Hi Eli,

Sorry, I am a bit lost here probably because of the different issues getting mixed. I will list down the different issue below and their status.

1. Bootloader_socAuthImage returns -1

I believe the suggestions to use SoC address and make sure the DAC is enabled resolves the issue. Let me know if this still fails.

2. TR Response failed for transfer : SRC = 0x601FF300, DST = 0x21000014, SIZE = 2064384

This issue is occuring with large images like ~3MB but does not for smaller size images ~105KB. Is this issue solved or still open?

3. Flash_read is failing

Is this issue still there?

Then, we have this new one:

Eli Mordel said:

When I reboot I get  Image loading done, switching to application ... but nothing happens 

I think the UART debug logs maybe disabled in the application. If they are enabled, can you please check the address at which the core is suspended after connecting via the debugger.

Regards,

Prashant

Hi Prashant,

Sorry for the many opened issues at once.

1. Haven't tried yet

2. Still continues but sometimes it writes  TR Response failed for transfer : SRC = 0x601FF300, DST = 0x21000014, SIZE = 2064384

and sometimes Image loading done, switching to application ...

3. I have a work around - It happens when I mix write and read of many chunks in a loop - so I skipped verification (read)

The most urgent and strange problem is that I think I copy the app into 0x80000 just as the python program via UART but for large file it doesn't work. 

Now I wrote a flash CRC utility - I'd like to compare what is the difference between the serial and my loader.

Please guide me to how do I : "check the address at which the core is suspended after connecting via the debugger."

Thanks,

Regards,

Eli

Hi Eli,

Thank you for the clarifications.

Eli Mordel said:

The most urgent and strange problem is that I think I copy the app into 0x80000 just as the python program via UART but for large file it doesn't work. 

Let's work on this first. If it doesn't work then do you know where exactly it fails? Also, have you tried following the same steps as the UART Uniflash for flashing?

Ideally, your flash utility should resemble the UART Uniflash at least from the back end perspective. The only difference should be the transport medium. Your flash utility receives the image over network then should follow the same bootloader flash APIs as used by UART Uniflash.

Eli Mordel said:

Please guide me to how do I : "check the address at which the core is suspended after connecting via the debugger."

Connect the debugger to your board -> Launch the target configuration -> Connect to the specific core like R5F0 (the core will have halted by the debugger) ->  Note down the address.

Regards,

Prashant

Hi Prashant,

I understand your suggestion .

I'll do the following steps : 

1. Compare CRC between network loaded file.hs_fs and UART loaded file.hs_fs

2. If it's the same I'll try to connect to target to see where it is stuck.

3. Discuss more option with you. 

Thanks,

Regards,

Eli

Hi Prashant,

I've completed my tests and I verify that on FLASH there's no difference (size, CRC) between the network and UART loaders.

Then I took some early version of my App ( 2282395 bytes) and managed to  load and run with my network loader .

So now I'm sure I've got a working network loader !

Now when I've added more code to my App - ( now it's 3081551 bytes)  still both loaders produce same CRC but

after power on  I get: Image loading done, switching to application ...

I'm trying to connect to target to see where it's stuck 

I did

-> Launch the target configuration

-> Connect to the specific core R5F0 

 -> Run->Load Symbols

-> Run

and then I do pause - but it doesn't pause.

Please advice.

Thanks,

Regards,

Eli

Hi Eli,

In working case, the memory contents at 0x0 (IVT) looks like this

The address 0x20 has the reset address aka the base address of the _c_int00 function. The control jumps to this address starting _c_int00 which in turn calls the main function.

However, when we looked at the memory content 0x0 of your non-working application after booting, it did not look right as the correct reset address was not there. This probably explains why your application boot fails.

So, we need to see why the IVT is not loading correctly at the location 0x0.

Please share the relevant application files as discussed in the meeting. I will once give them a try and see if I have the same behaviour.

Regards,

Prashant

Hi Prashant,

Yes I will attach the out the hs_fs and the map files.

Thanks,

Regards,

Eli

Hi Prashant,

This is the memory browser picture at address=0

It's not 0 but still it's stuck.

Thanks,

Regards,

Eli

Hi Eli,

There are two things wrong in the shared memory content:

1 => The first word (4B) seems to contain 0xFEDCBA98 which is not expected. The value should have been 0xE59FF018.

2=> There are no addresses available starting the location 0x20. As I said, the location 0x20 will have your reset address but here it's 0x0.

Probably something is overwriting these locations or maybe SBL itself is not loading them correctly. Can you please confirm if there are any changes in the SBL OSPI example you are using?

Regards,

Prashant

Hi Eli,

The issue is reproducible with the shared images as shown

I will debug through it and update asap.

Regards,

Prashant

Hi Prashant,

Would you like me to share my  SBL project with you ?

Regards,

Eli

Hi Eli,

Thanks for asking. But since I have reproduced the issue with my SBL, I think I won't be needing your SBL project.

In fact, I debugged the issue a bit and it seems the loading of the images itself fails. The SBL doesn't get the chance to self reset the core and jump to the loaded application.

I will debug the issue more tomorrow and provide details if I have more information about the root cause.

Regards,

Prashant

Hi Eli,

I have done the full debugging of the issue finding the root cause and the fix as well. The root cause is that the XIP generator tool, which is called in the build process, is generating corrupt RPRC image which leads to the boot failure.

Since, we are not using XIP here, the fix would be to just comment or delete the lines in the makefile that calls the XIP generator tool. I assume that you are using the CCS to build your GCC TCP example. If yes then please comment or delete the following exact lines from the CCS post-build makefile (makefile_ccs_bootimage_gen)

$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)

Then rebuild the project and reflash. The example should be up and running now.

Regards,

Prashant

Hi Eli,

With that fix, I generated the updated appimage from the shared TCP .out image and it was successfully booted.

Following is the CCS screenshot showing the memory contents at 0x0 looking right and also the core is halted at some address in the DDR which is also expected.

In fact, I even got the UART logs from the TCP application

Regards,

Prashant

Hi Prashant,

Here is a copy of my post build steps 

$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MCU_PLUS_SDK_PATH=${MCU_PLUS_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x

What should be commented out and what should be added ?

Thanks,

Regards,

Eli

Hi Eli,

This post build steps is using the makefile named makefile_ccs_bootimage_gen. Please open this file in any text editor and delete the following lines (there is nothing to be added).

$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)

Taking Hello World example as an example, the difference would look like this (left shows red lines which are deleted)

Regards,

Prashant

Hi Prashant,

Here is my post build makefile - which lines to comment out ?

#
# Auto generated makefile
#

# Below variables need to be defined outside this file or via command line
# - MCU_PLUS_SDK_PATH
# - PROFILE
# - CG_TOOL_ROOT
# - OUTNAME
# - CCS_INSTALL_DIR
# - CCS_IDE_MODE

CCS_PATH=$(CCS_INSTALL_DIR)
include $(MCU_PLUS_SDK_PATH)/imports.mak
include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak

STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif

OUTFILE=$(PROFILE)/$(OUTNAME).out
BOOTIMAGE_PATH=$(abspath ${PROFILE})
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
PERL=C:/Strawberry/perl/bin/perl.exe
PATCH_SCRIPT=$(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/eli_patch_exidx_for_out2rprc.pl
PATCH_TEMP_OUT_FILE=$(PROFILE)/patch_stdout_$(PROFILE).txt
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt

BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55

MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py

ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
endif

MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
$(PERL) $(PATCH_SCRIPT) $(OUTFILE) > $(PATCH_TEMP_OUT_FILE)
$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
$(RM) $(BOOTIMAGE_NAME)-enc
endif
endif
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
@echo .
ifeq ($(DEVICE_TYPE),HS)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
@echo .
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
endif
endif

Thanks,

Regards,

Eli.

Hi Eli,

I copied the contents and marked the lines that needs to be commented out with 5#'s at the start of the line. Simply search for '#####' to find these lines

#
# Auto generated makefile
#

# Below variables need to be defined outside this file or via command line
# - MCU_PLUS_SDK_PATH
# - PROFILE
# - CG_TOOL_ROOT
# - OUTNAME
# - CCS_INSTALL_DIR
# - CCS_IDE_MODE

CCS_PATH=$(CCS_INSTALL_DIR)
include $(MCU_PLUS_SDK_PATH)/imports.mak
include $(MCU_PLUS_SDK_PATH)/devconfig/devconfig.mak

STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif

OUTFILE=$(PROFILE)/$(OUTNAME).out
BOOTIMAGE_PATH=$(abspath ${PROFILE})
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
PERL=C:/Strawberry/perl/bin/perl.exe
PATCH_SCRIPT=$(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/eli_patch_exidx_for_out2rprc.pl
PATCH_TEMP_OUT_FILE=$(PROFILE)/patch_stdout_$(PROFILE).txt
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt

BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55

MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MCU_PLUS_SDK_PATH)/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MCU_PLUS_SDK_PATH)/tools/boot/signing/appimage_x509_cert_gen.py

ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MCU_PLUS_SDK_PATH)/tools/boot/xipGen/xipGen.out
endif

MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
$(PERL) $(PATCH_SCRIPT) $(OUTFILE) > $(PATCH_TEMP_OUT_FILE)
$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
##### $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
##### $(RM) $(BOOTIMAGE_RPRC_NAME)
##### $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
##### $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
$(RM) $(BOOTIMAGE_NAME)-enc
endif
endif
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
@echo .
ifeq ($(DEVICE_TYPE),HS)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
@echo .
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
endif
endif

Regards,

Prashant

Hi Prashant,

When I comment these lines I get 

makefile_ccs_bootimage_gen:77: recipe for target 'all' failed
process_begin: CreateProcess(NULL, ##### eli + prashant C:\ti\ccs1250\ccs/utils/cygwin/cp C:/Maxx_Firmware/projects/am2432/Debug__GNU/tcpserver_freertos_freertos_fat_timer_gcc.rprc C:/Maxx_Firmware/projects/am2432/Debug__GNU/tcpserver_freertos_freertos_fat_timer_gcc.rprc_tmp, ...) failed.

gmake[3]: *** [all] Error 2
makefile:409: recipe for target 'post-build' failed

So the hs_fs file is not created !

Maybe we have to replace these lines with something else ?

Thanks,

Regards,

Eli.

Hi Eli,

Eli Mordel said:

process_begin: CreateProcess(NULL, ##### eli + prashant C:\ti\ccs1250\ccs/utils/cygwin/cp

The makefile is not treating the lines as comments. Please make sure the #'s starts at the very start of the line to be treated as comments.

Something like this:

Regards,

Prashant