Original question:
Hi,
Since we are dealing safety critical systems, we were asked to provide SEE upset rate for the part TMS570LS3137TMEP.
One recent thread says it is not available for this part.
And there is an old thread that says TI can share based on NDA
Could anyone give some clarity or information on this.
Thanks,
Jaiganesh
Jaiganesh,
The consequences of SEU include temporary data loss in memories and transistor latch-up, etc. The errors associated with SEU do not cause system destruction and they can be recovered by rewriting the data. The memory (flash, RAM) on TMS570 is protected by ECC for single bit upsets. Bit multiplexing or bit interleaving where bits in the same logical word are physically separated is employed to minimize multibit errors in the same word.
<-- Device Safety Manual
We don't SEU report for TMS570LS3137 device. But we have SEU test report for TMS570LC4357-SEP BGA package
HI Jai,
There are two 128-bit instruction buffers and two 128-bit data buffers in flash wrapper. A total of eight 32-bit instructions and eight 32-bit data can be stored in the buffers at the same time.
The Flash wrapper contains an embedded SECDED (Single Error Correction and Double Error Detection) circuit. SECDED when enabled provides capability to screen out memory faults and correct the fault. SECDED requires a total of eight ECC check bits associated with each 64 bit wide data word and its corresponding address. During read operation, the 19 address bits together with the 64-bit data read out of flash banks pass through the ECC check bit generator to produce the 8 check bits. These eight calculated ECC check bits are then XORed with the stored check bits associated with the address and the read data.
The corrected instruction and data are stored in the instruction buffers and data buffers in flash wrapper. CPU reads instruction and data from those buffers.
