AM2634: am2634

Tej_1441

Part Number: AM2634
Other Parts Discussed in Thread: SYSCONFIG, LP-AM263

Hii,

I am sampling adc sine wave ( soc from software ) with amplitude(high=1v and low=0v) with frequency of 1mhz but i am getting digital value between 2300 and 2450 . i should be gettiing from 0 to something?
what can be possible error??

over 1 year ago

0 Kier over 1 year ago

Mastermind 8025 points

Do you mean 1mHz (0.001Hz) or do you mean 1MHz? If the latter I would say aliasing is the problem. What do you get at 0Hz and 1kHz for example?

0 Tej_1441 over 1 year ago in reply to Kier

Prodigy 160 points

i meant it to be 1MHz.
it give fine for 1Hz to 5Hz, But for 1KHz and above it is not giving correct.
how to solve this problem??

0 Kier over 1 year ago in reply to Tej_1441

Mastermind 8025 points

The obvious question: What is your sampling rate?

0 Tej_1441 over 1 year ago in reply to Kier

Prodigy 160 points

For am2634 launchpad it is supposed to be 4msps??

+1 Kier over 1 year ago in reply to Tej_1441

Mastermind 8025 points

The sampling period is what you program it to be.

Have you experimented with the examples yet?: C:\ti\mcu_plus_sdk_am263x_08_05_00_24\examples\drivers\adc

0 Tej_1441 over 1 year ago in reply to Kier

Prodigy 160 points

have set it to 4msps with syscfg.
Do i need to change it manually in code ??

0 Kier over 1 year ago in reply to Tej_1441

Mastermind 8025 points

The Start Of Conversion (SOC) is mostly configured in SYSCONFIG. Study the examples in combination with the TRM.

0 Tej_1441 over 1 year ago in reply to Kier

Prodigy 160 points

In Start Of Conversion(SOC) from software, are SYSCLK, ADC Clock Prescaler and SOCx Sample Window are enough for setting the sampling rate or do we need to initialize other driver like EPWM, because example in sdk for SOC from Software is only using SYSCLK for time reference for adc ??

0 Kier over 1 year ago in reply to Tej_1441

Mastermind 8025 points

The ADC can be triggered in many different ways as mentioned in the manual:

EPWM is just one option. The readme for your example is clear enough I think.

In this case, the sample rate is the rate at which ADC_forceSOC() is called:

0 Tej_1441 over 1 year ago in reply to Kier

Prodigy 160 points

hii kier,

I am using a sampling rate of greater than 3 msps ( SysClk=200MHz AdcClock=200/3 MHz ).
I am feeding the square wave of 1MHz to the J1/J3 Pin 23 of am2634 launchpad in Continuous mode but still i am getting data in range 1200 to 1400.

This is code for taking the digital data in SOC from Software.

while(1)
{

ADC_clearInterruptStatus(baseAddr, ADC_INT_NUMBER1);

ADC_forceSOC(baseAddr, ADC_SOC_NUMBER0);
while(ADC_getInterruptStatus(baseAddr, ADC_INT_NUMBER1) == false)
{
}
DebugP_log("ADC Result register value : %d\r\n", ADC_readResult(CONFIG_ADC0_RESULT_BASE_ADDR, ADC_SOC_NUMBER0));

}

pls suggest how to fix it.

0 Kier over 1 year ago in reply to Tej_1441

Mastermind 8025 points

When you say "fix it", you mean you want to achieve a sample rate of 4MSPS such that you can reliably reconstruct a 1MHz sine wave?

When you say "i am getting data", how are you viewing this data?

If you are just using the code above then the sample rate is only as fast as the call to ADC_forceSOC(). One of the problems could be that DebugP_log is a very slow process so the call frequency of ADC_forceSOC() will be low I imagine.

Comment out DebugP_log() and instead set-up a buffer to store the return value of ADC_readResult() but you will need quite a lot of memory. Then use the Graph feature to plot the data points:

Sorry but I'm not TI support staff so cannot afford to spend much more time on this. Hopefully TI will pick up this topic.

0 Fleenor over 1 year ago in reply to Kier

TI__Mastermind 20212 points

Hello Tej_1441, Kier,

I'll start by giving Kier a great Thank You for providing great initial feedback here.

I am glad to continue further support as needed.

Tej, where are you at now with your project?

Best Regards,

Zackary Fleenor

0 Fleenor over 1 year ago in reply to Fleenor

TI__Mastermind 20212 points

Based on the information I have gathered so far; I think a signal conditioning circuit needs to be included in the test setup. What instrumentation is being used to inject the 1 MHz sine wave? It will need sufficient drive strength to charge the S&H capacitor. The following app note is also applicable to the AM263x SAR ADC.

https://www.ti.com/lit/an/spract6a/spract6a.pdf

0 Tej_1441 over 1 year ago in reply to Fleenor

Prodigy 160 points

hii fleener , thanks for your reply
I am using function generator for generating the 1MHz sine wave.

+1 Fleenor over 1 year ago in reply to Tej_1441

TI__Mastermind 20212 points

Can you provide any spec details for the function generator signal? Is a signal conditioning circuit like I mentioned above something that could be done here?

0 Tej_1441 11 months ago in reply to Fleenor

Prodigy 160 points

Hii Fleenor,
sorry for late reply as i was busy with some other works.
i have planned to do adc sampling with epwm as the trigger source for SOC, But even with this case i am stuck in similar situation, where i am able to sample signal of sine wave(amplitude 1VPP and offset 0.5V) till 50 KHz but when i increase frequency of signal then it is getting distorted and upper and lower values missing.

GRAPH at 150KHz.

Here is code for initilization of adc and epwm driver.

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#include "ti_drivers_open_close.h"
#include <kernel/dpl/DebugP.h>
void Drivers_open(void)
{
Drivers_adcOpen();
Drivers_epwmOpen();
Drivers_intXbarOpen();
Drivers_uartOpen();
}
void Drivers_close(void)
{
Drivers_uartClose();
}
void Drivers_adcOpen()
{
/* CONFIG_ADC1 initialization */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

#include "ti_drivers_open_close.h"
#include <kernel/dpl/DebugP.h>

void Drivers_open(void)
{

Drivers_adcOpen();
Drivers_epwmOpen();
Drivers_intXbarOpen();
Drivers_uartOpen();
}

void Drivers_close(void)
{
Drivers_uartClose();
}

void Drivers_adcOpen()
{
/* CONFIG_ADC1 initialization */

/* Configures the analog-to-digital converter module prescaler. */
ADC_setPrescaler(CONFIG_ADC1_BASE_ADDR, ADC_CLK_DIV_3_0);
/* Configures the analog-to-digital converter resolution and signal mode. */
ADC_setMode(CONFIG_ADC1_BASE_ADDR, ADC_RESOLUTION_12BIT, ADC_MODE_SINGLE_ENDED);
/* Sets the priority mode of the SOCs. */
ADC_setSOCPriority(CONFIG_ADC1_BASE_ADDR, ADC_PRI_ALL_ROUND_ROBIN);

/* Start of Conversion 0 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 0, ADC_TRIGGER_EPWM0_SOCA, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 0, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 1 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 1, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 1, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 2 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 2, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 2, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 3 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 3, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 3, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 4 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 4, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 4, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 5 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 5, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 5, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 6 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 6, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 6, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 7 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 7, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 7, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 8 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 8, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 8, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 9 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 9, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 9, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 10 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 10, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 10, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 11 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 11, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 11, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 12 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 12, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 12, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 13 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 13, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 13, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 14 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 14, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 14, ADC_INT_SOC_TRIGGER_NONE);

/* Start of Conversion 15 Configuration */
/* Configures a start-of-conversion (SOC) in the ADC. */
ADC_setupSOC(CONFIG_ADC1_BASE_ADDR, 15, ADC_TRIGGER_SW_ONLY, ADC_CH_ADCIN0, 16);
/* Configures the interrupt SOC trigger of an SOC. */
ADC_setInterruptSOCTrigger(CONFIG_ADC1_BASE_ADDR, 15, ADC_INT_SOC_TRIGGER_NONE);

/* Powers up the analog-to-digital converter core. */
ADC_enableConverter(CONFIG_ADC1_BASE_ADDR);
/* Delay for ADC to power up. */
ClockP_usleep(500);
/* Sets the timing of the end-of-conversion pulse */
ADC_setInterruptPulseMode(CONFIG_ADC1_BASE_ADDR, ADC_PULSE_END_OF_ACQ_WIN);


/* ADC Interrupt 1 Configuration */
/* Enables an ADC interrupt source. */
ADC_enableInterrupt(CONFIG_ADC1_BASE_ADDR, 0);
/* Sets the source EOC for an analog-to-digital converter interrupt. */
ADC_setInterruptSource(CONFIG_ADC1_BASE_ADDR, 0, ADC_SOC_NUMBER0);
/* Enables continuous mode for an ADC interrupt. */
ADC_enableContinuousMode(CONFIG_ADC1_BASE_ADDR, 0);

/* ADC Interrupt 2 Configuration */
/* Disables an ADC interrupt source. */
ADC_disableInterrupt(CONFIG_ADC1_BASE_ADDR, 1);
/* Sets the source EOC for an analog-to-digital converter interrupt. */
ADC_setInterruptSource(CONFIG_ADC1_BASE_ADDR, 1, ADC_SOC_NUMBER0);
/* Disables continuous mode for an ADC interrupt. */
ADC_disableContinuousMode(CONFIG_ADC1_BASE_ADDR, 1);

/* ADC Interrupt 3 Configuration */
/* Disables an ADC interrupt source. */
ADC_disableInterrupt(CONFIG_ADC1_BASE_ADDR, 2);
/* Sets the source EOC for an analog-to-digital converter interrupt. */
ADC_setInterruptSource(CONFIG_ADC1_BASE_ADDR, 2, ADC_SOC_NUMBER0);
/* Disables continuous mode for an ADC interrupt. */
ADC_disableContinuousMode(CONFIG_ADC1_BASE_ADDR, 2);

/* ADC Interrupt 4 Configuration */
/* Disables an ADC interrupt source. */
ADC_disableInterrupt(CONFIG_ADC1_BASE_ADDR, 3);
/* Sets the source EOC for an analog-to-digital converter interrupt. */
ADC_setInterruptSource(CONFIG_ADC1_BASE_ADDR, 3, ADC_SOC_NUMBER0);
/* Disables continuous mode for an ADC interrupt. */
ADC_disableContinuousMode(CONFIG_ADC1_BASE_ADDR, 3);


/* Post Processing Block 1 Configuration */
/* Configures a post-processing block (PPB) in the ADC. */
ADC_setupPPB(CONFIG_ADC1_BASE_ADDR, 0, ADC_SOC_NUMBER0);
/* Disables individual ADC PPB event sources. */
ADC_disablePPBEvent(CONFIG_ADC1_BASE_ADDR, 0, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Disables individual ADC PPB event interrupt sources. */
ADC_disablePPBEventInterrupt(CONFIG_ADC1_BASE_ADDR, 0, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Sets the post processing block offset correction. */
ADC_setPPBCalibrationOffset(CONFIG_ADC1_BASE_ADDR, 0, 0);
/* Sets the post processing block reference offset. */
ADC_setPPBReferenceOffset(CONFIG_ADC1_BASE_ADDR, 0, 0);
/* Disables two's complement capability in the PPB. */
ADC_disablePPBTwosComplement(CONFIG_ADC1_BASE_ADDR, 0);
/* Sets the windowed trip limits for a PPB. */
ADC_setPPBTripLimits(CONFIG_ADC1_BASE_ADDR, 0, 0, 0);
/* Disables cycle by cycle clear of ADC PPB event flags. */
ADC_disablePPBEventCBCClear(CONFIG_ADC1_BASE_ADDR, 0);

/* Post Processing Block 2 Configuration */
/* Configures a post-processing block (PPB) in the ADC. */
ADC_setupPPB(CONFIG_ADC1_BASE_ADDR, 1, ADC_SOC_NUMBER0);
/* Disables individual ADC PPB event sources. */
ADC_disablePPBEvent(CONFIG_ADC1_BASE_ADDR, 1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Disables individual ADC PPB event interrupt sources. */
ADC_disablePPBEventInterrupt(CONFIG_ADC1_BASE_ADDR, 1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Sets the post processing block offset correction. */
ADC_setPPBCalibrationOffset(CONFIG_ADC1_BASE_ADDR, 1, 0);
/* Sets the post processing block reference offset. */
ADC_setPPBReferenceOffset(CONFIG_ADC1_BASE_ADDR, 1, 0);
/* Disables two's complement capability in the PPB. */
ADC_disablePPBTwosComplement(CONFIG_ADC1_BASE_ADDR, 1);
/* Sets the windowed trip limits for a PPB. */
ADC_setPPBTripLimits(CONFIG_ADC1_BASE_ADDR, 1, 0, 0);
/* Disables cycle by cycle clear of ADC PPB event flags. */
ADC_disablePPBEventCBCClear(CONFIG_ADC1_BASE_ADDR, 1);

/* Post Processing Block 3 Configuration */
/* Configures a post-processing block (PPB) in the ADC. */
ADC_setupPPB(CONFIG_ADC1_BASE_ADDR, 2, ADC_SOC_NUMBER0);
/* Disables individual ADC PPB event sources. */
ADC_disablePPBEvent(CONFIG_ADC1_BASE_ADDR, 2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Disables individual ADC PPB event interrupt sources. */
ADC_disablePPBEventInterrupt(CONFIG_ADC1_BASE_ADDR, 2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Sets the post processing block offset correction. */
ADC_setPPBCalibrationOffset(CONFIG_ADC1_BASE_ADDR, 2, 0);
/* Sets the post processing block reference offset. */
ADC_setPPBReferenceOffset(CONFIG_ADC1_BASE_ADDR, 2, 0);
/* Disables two's complement capability in the PPB. */
ADC_disablePPBTwosComplement(CONFIG_ADC1_BASE_ADDR, 2);
/* Sets the windowed trip limits for a PPB. */
ADC_setPPBTripLimits(CONFIG_ADC1_BASE_ADDR, 2, 0, 0);
/* Disables cycle by cycle clear of ADC PPB event flags. */
ADC_disablePPBEventCBCClear(CONFIG_ADC1_BASE_ADDR, 2);

/* Post Processing Block 4 Configuration */
/* Configures a post-processing block (PPB) in the ADC. */
ADC_setupPPB(CONFIG_ADC1_BASE_ADDR, 3, ADC_SOC_NUMBER0);
/* Disables individual ADC PPB event sources. */
ADC_disablePPBEvent(CONFIG_ADC1_BASE_ADDR, 3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Disables individual ADC PPB event interrupt sources. */
ADC_disablePPBEventInterrupt(CONFIG_ADC1_BASE_ADDR, 3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
/* Sets the post processing block offset correction. */
ADC_setPPBCalibrationOffset(CONFIG_ADC1_BASE_ADDR, 3, 0);
/* Sets the post processing block reference offset. */
ADC_setPPBReferenceOffset(CONFIG_ADC1_BASE_ADDR, 3, 0);
/* Disables two's complement capability in the PPB. */
ADC_disablePPBTwosComplement(CONFIG_ADC1_BASE_ADDR, 3);
/* Sets the windowed trip limits for a PPB. */
ADC_setPPBTripLimits(CONFIG_ADC1_BASE_ADDR, 3, 0, 0);
/* Disables cycle by cycle clear of ADC PPB event flags. */
ADC_disablePPBEventCBCClear(CONFIG_ADC1_BASE_ADDR, 3);

/* Set SOC burst mode. */
ADC_setBurstModeConfig(CONFIG_ADC1_BASE_ADDR, ADC_TRIGGER_SW_ONLY, 1);
/* Disables SOC burst mode. */
ADC_disableBurstMode(CONFIG_ADC1_BASE_ADDR);
}

void Drivers_epwmOpen(void)
{
/* CONFIG_EPWM0 initialization */

/* Time Base */
EPWM_setEmulationMode(CONFIG_EPWM0_BASE_ADDR, EPWM_EMULATION_STOP_AFTER_NEXT_TB);
EPWM_setClockPrescaler(CONFIG_EPWM0_BASE_ADDR, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(CONFIG_EPWM0_BASE_ADDR, 199);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_TBPRD_TBPRDHR);
EPWM_setPeriodLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_PERIOD_SHADOW_LOAD);
EPWM_selectPeriodLoadEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO);
EPWM_setTimeBaseCounter(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setTimeBaseCounterMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_MODE_UP);
EPWM_setCountModeAfterSync(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNT_MODE_DOWN_AFTER_SYNC);
EPWM_disablePhaseShiftLoad(CONFIG_EPWM0_BASE_ADDR);
EPWM_setPhaseShift(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_enableSyncOutPulseSource(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setSyncInPulseSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SYNC_IN_PULSE_SRC_DISABLE);
EPWM_setOneShotSyncOutTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_OSHT_SYNC_OUT_TRIG_SYNC);

HRPWM_setSyncPulseSource(CONFIG_EPWM0_BASE_ADDR, HRPWM_PWMSYNC_SOURCE_PERIOD);

/* Counter Compare */
EPWM_setCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_A, 100);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_CMPA_CMPAHR);

EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_B, 0);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_CMPB_CMPBHR);

EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_C, 0);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_CMPC);

EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_D, 0);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_CMPD);

EPWM_setCounterCompareShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_COMPARE_D, EPWM_COMP_LOAD_ON_CNTR_ZERO);

/* Action Qualifier */
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_AQCSFRC);
EPWM_setActionQualifierContSWForceShadowMode(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_AQCTLA_AQCTLA2);
EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_ACTION_QUALIFIER_A);
EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_ACTION_QUALIFIER_A, EPWM_AQ_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierT1TriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1);
EPWM_setActionQualifierT2TriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1);
EPWM_setActionQualifierSWAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE);
EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_SW_DISABLED);
EPWM_disableGlobalLoadRegisters(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_REGISTER_AQCTLB_AQCTLB2);
EPWM_disableActionQualifierShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_ACTION_QUALIFIER_B);
EPWM_setActionQualifierShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_ACTION_QUALIFIER_B, EPWM_AQ_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierSWAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE);
EPWM_setActionQualifierContSWForceAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_SW_DISABLED);

/* Events */
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);
EPWM_setActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN);

/* Trip Zone */
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_HIGH_Z);
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_HIGH_Z);
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_HIGH_Z);
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_HIGH_Z);
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_HIGH_Z);
EPWM_setTripZoneAction(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_HIGH_Z);
EPWM_disableTripZoneAdvAction(CONFIG_EPWM0_BASE_ADDR);
EPWM_enableTripZoneSignals(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_enableTripZoneSignals(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_selectCycleByCycleTripZoneClearEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO);
EPWM_enableTripZoneInterrupt(CONFIG_EPWM0_BASE_ADDR, 0);

/* Digital Compare */
EPWM_setDigitalCompareFilterInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_WINDOW_SOURCE_DCAEVT1);
EPWM_disableDigitalCompareBlankingWindow(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDigitalCompareBlankingEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_WINDOW_START_TBCTR_PERIOD, 0);
EPWM_setDigitalCompareWindowOffset(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setDigitalCompareWindowLength(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_disableDigitalCompareWindowInverseMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_disableDigitalCompareCounterCapture(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDigitalCompareCounterShadowMode(CONFIG_EPWM0_BASE_ADDR, false);
EPWM_disableDigitalCompareEdgeFilter(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDigitalCompareEdgeFilterMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_EDGEFILT_MODE_RISING);
EPWM_setDigitalCompareEdgeFilterEdgeCount(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_EDGEFILT_EDGECNT_0);
EPWM_disableValleyCapture(CONFIG_EPWM0_BASE_ADDR);
EPWM_setValleyTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE);

EPWM_setValleyTriggerEdgeCounts(CONFIG_EPWM0_BASE_ADDR, 0, 0);
EPWM_disableValleyHWDelay(CONFIG_EPWM0_BASE_ADDR);
EPWM_setValleySWDelayValue(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setValleyDelayDivider(CONFIG_EPWM0_BASE_ADDR, EPWM_VALLEY_DELAY_MODE_SW_DELAY);
EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM0_BASE_ADDR, 0, EPWM_DC_TYPE_DCAH);
EPWM_selectDigitalCompareTripInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAH);
EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM0_BASE_ADDR, 0, EPWM_DC_TYPE_DCAL);
EPWM_selectDigitalCompareTripInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCAL);
EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DC_DISABLED);
EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DC_DISABLED);
EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A);

EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED);
EPWM_setDigitalCompareEventSource(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED);
EPWM_setDigitalCompareEventSource(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM0_BASE_ADDR, 0, EPWM_DC_TYPE_DCBH);
EPWM_selectDigitalCompareTripInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBH);
EPWM_enableDigitalCompareTripCombinationInput(CONFIG_EPWM0_BASE_ADDR, 0, EPWM_DC_TYPE_DCBL);
EPWM_selectDigitalCompareTripInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_TRIP_TRIPIN1, EPWM_DC_TYPE_DCBL);
EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DC_DISABLED);
EPWM_setTripZoneDigitalCompareEventCondition(CONFIG_EPWM0_BASE_ADDR, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DC_DISABLED);

EPWM_disableDigitalCompareADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B);

EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_SYNCED);
EPWM_setDigitalCompareEventSource(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_setDigitalCompareEventSyncMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_SYNCED);
EPWM_setDigitalCompareEventSource(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED);
EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO);
EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED);
EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO);
EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_DISABLED);
EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO);
EPWM_setDigitalCompareCBCLatchMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_DISABLED);
EPWM_selectDigitalCompareCBCLatchClearEvent(CONFIG_EPWM0_BASE_ADDR, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO);

/* Deadband */
EPWM_disableDeadBandControlShadowLoadMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDeadBandControlShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_LOAD_ON_CNTR_ZERO);
EPWM_setRisingEdgeDeadBandDelayInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_INPUT_EPWMA);
EPWM_setFallingEdgeDeadBandDelayInput(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_INPUT_EPWMA);
EPWM_setDeadBandDelayPolarity(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
EPWM_setDeadBandDelayPolarity(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_HIGH);
EPWM_setDeadBandDelayMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_RED, false);
EPWM_setDeadBandDelayMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_FED, false);
EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_OUTPUT_A, false);
EPWM_setDeadBandOutputSwapMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_OUTPUT_B, false);


EPWM_disableRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_setRisingEdgeDelayCountShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_RED_LOAD_ON_CNTR_ZERO);
EPWM_setRisingEdgeDelayCount(CONFIG_EPWM0_BASE_ADDR, 0);

EPWM_disableFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_setFallingEdgeDelayCountShadowLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_FED_LOAD_ON_CNTR_ZERO);
EPWM_setFallingEdgeDelayCount(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setDeadBandCounterClock(CONFIG_EPWM0_BASE_ADDR, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);

/* Chopper */
EPWM_disableChopper(CONFIG_EPWM0_BASE_ADDR);
EPWM_setChopperDutyCycle(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setChopperFreq(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setChopperFirstPulseWidth(CONFIG_EPWM0_BASE_ADDR, 0);

/* Event Trigger */
EPWM_disableInterrupt(CONFIG_EPWM0_BASE_ADDR);
EPWM_setInterruptSource(CONFIG_EPWM0_BASE_ADDR, EPWM_INT_TBCTR_ZERO, 0);
EPWM_setInterruptEventCount(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_disableInterruptEventCountInit(CONFIG_EPWM0_BASE_ADDR);
EPWM_setInterruptEventCountInitValue(CONFIG_EPWM0_BASE_ADDR, 0);

EPWM_enableADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
EPWM_setADCTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO, 0);
EPWM_setADCTriggerEventPrescale(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, 1);
EPWM_enableADCTriggerEventCountInit(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, 0);

EPWM_disableADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_B);
EPWM_setADCTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_B, EPWM_SOC_DCxEVT1, EPWM_SOC_DCxEVT1);
EPWM_setADCTriggerEventPrescale(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_B, 0);
EPWM_disableADCTriggerEventCountInit(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_B);
EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_B, 0);

/* XCMP Mode */
EPWM_disableXCMPMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_disableSplitXCMP(CONFIG_EPWM0_BASE_ADDR);
EPWM_allocAXCMP(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_NONE_CMPA);
EPWM_setXCMPLoadMode(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE);
EPWM_setXCMPShadowLevel(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWLEVEL_0);
EPWM_setXCMPShadowBufPtrLoadOnce(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL);
EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, 0);
EPWM_setXCMPShadowRepeatBufxCount(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, 0);

/* Write values to Reg */
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP1_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP2_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP3_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP4_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP5_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP6_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP7_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP8_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP1_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP2_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP3_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP4_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP5_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP6_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP7_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP8_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP1_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP2_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP3_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP4_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP5_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP6_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP7_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP8_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP1_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP2_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP3_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP4_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP5_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP6_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP7_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP8_SHADOW3, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XTBPRD_ACTIVE, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XTBPRD_SHADOW1, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XTBPRD_SHADOW2, 0);
EPWM_setXCMPRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XTBPRD_SHADOW3, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMIN_ACTIVE, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMAX_ACTIVE, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMIN_SHADOW1, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMAX_SHADOW1, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMIN_SHADOW2, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMAX_SHADOW2, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMIN_SHADOW3, 0);
EPWM_setXMINMAXRegValue(CONFIG_EPWM0_BASE_ADDR, EPWM_XMAX_SHADOW3, 0);

/* Events */

EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_ACTIVE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW1, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW2, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7);
EPWM_setXCMPActionQualifierAction(CONFIG_EPWM0_BASE_ADDR, EPWM_XCMP_SHADOW3, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8);

/* Diode Emulation */
EPWM_disableDiodeEmulationMode(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDiodeEmulationMode(CONFIG_EPWM0_BASE_ADDR, EPWM_DIODE_EMULATION_CBC);
EPWM_setDiodeEmulationReentryDelay(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPL);
EPWM_configureDiodeEmulationTripSources(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0, EPWM_DE_TRIPH);
EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_SYNC_TRIPHorL);
EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_CHANNEL_A, EPWM_DE_TRIPL);
EPWM_selectDiodeEmulationPWMsignal(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_SYNC_TRIPHorL);
EPWM_selectDiodeEmulationTripSignal(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_CHANNEL_B, EPWM_DE_TRIPL);
EPWM_nobypassDiodeEmulationLogic(CONFIG_EPWM0_BASE_ADDR);

EPWM_disableDiodeEmulationMonitorModeControl(CONFIG_EPWM0_BASE_ADDR);
EPWM_setDiodeEmulationMonitorCounterThreshold(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_COUNT_DOWN, 0);
EPWM_setDiodeEmulationMonitorModeStep(CONFIG_EPWM0_BASE_ADDR, EPWM_DE_COUNT_UP, 0);

/* HRPWM */
HRPWM_disableAutoConversion(CONFIG_EPWM0_BASE_ADDR);
HRPWM_setMEPControlMode(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
HRPWM_setMEPControlMode(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);
HRPWM_setHiResPhaseShift(CONFIG_EPWM0_BASE_ADDR, 0);
HRPWM_disablePhaseShiftLoad(CONFIG_EPWM0_BASE_ADDR);
HRPWM_setMEPEdgeSelect(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_DISABLE);
HRPWM_setMEPEdgeSelect(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_DISABLE);
HRPWM_setHiResCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, HRPWM_COUNTER_COMPARE_A, 1);
HRPWM_setHiResCounterCompareValue(CONFIG_EPWM0_BASE_ADDR, HRPWM_COUNTER_COMPARE_B, 1);
HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO);
HRPWM_setCounterCompareShadowLoadEvent(CONFIG_EPWM0_BASE_ADDR, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO);
HRPWM_disablePeriodControl(CONFIG_EPWM0_BASE_ADDR);
HRPWM_setHiResTimeBasePeriod(CONFIG_EPWM0_BASE_ADDR, 0);
HRPWM_setDeadbandMEPEdgeSelect(CONFIG_EPWM0_BASE_ADDR, HRPWM_DB_MEP_CTRL_DISABLE);
HRPWM_setHiResRisingEdgeDelay(CONFIG_EPWM0_BASE_ADDR, 0);
HRPWM_setRisingEdgeDelayLoadMode(CONFIG_EPWM0_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO);
HRPWM_setHiResFallingEdgeDelayOnly(CONFIG_EPWM0_BASE_ADDR, 0);
HRPWM_setFallingEdgeDelayLoadMode(CONFIG_EPWM0_BASE_ADDR, HRPWM_LOAD_ON_CNTR_ZERO);
HRPWM_setOutputSwapMode(CONFIG_EPWM0_BASE_ADDR, false);
HRPWM_setChannelBOutputPath(CONFIG_EPWM0_BASE_ADDR, HRPWM_OUTPUT_ON_B_NORMAL);

/* ICL */
EPWM_disableIllegalComboLogic(CONFIG_EPWM0_BASE_ADDR, EPWM_MINDB_BLOCK_A);
EPWM_disableIllegalComboLogic(CONFIG_EPWM0_BASE_ADDR, EPWM_MINDB_BLOCK_B);

/* MDL */
EPWM_disableMinimumDeadBand(CONFIG_EPWM0_BASE_ADDR, EPWM_MINDB_BLOCK_A);
EPWM_disableMinimumDeadBand(CONFIG_EPWM0_BASE_ADDR, EPWM_MINDB_BLOCK_B);
/* Global Load */
EPWM_disableGlobalLoad(CONFIG_EPWM0_BASE_ADDR);
EPWM_setGlobalLoadTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_GL_LOAD_PULSE_CNTR_ZERO);
EPWM_setGlobalLoadEventPrescale(CONFIG_EPWM0_BASE_ADDR, 0);
EPWM_disableGlobalLoadOneShotMode(CONFIG_EPWM0_BASE_ADDR);

/* EPWM Module */
EPWM_lockRegisters(CONFIG_EPWM0_BASE_ADDR, 0);
}

void Drivers_intXbarOpen()
{
/* INT XBAR */
SOC_xbarSelectInterruptXBarInputSource(CSL_CONTROLSS_INTXBAR_U_BASE, 0, 0, 0, ( INT_XBAR_ADC1_INT1 ), 0, 0, 0, 0);
}

/*
* UART
*/

/* UART Driver handles */
UART_Handle gUartHandle[CONFIG_UART_NUM_INSTANCES];

#include <drivers/uart/v0/lld/dma/uart_dma.h>
#include <kernel/dpl/ClockP.h>
#include <drivers/edma.h>
/* EDMA driver confiurations */
EDMA_Config gEdmaConfig[] =
{
};

uint32_t gEdmaConfigNum = 0;

UART_DmaChConfig gUartDmaChConfig[CONFIG_UART_NUM_INSTANCES] =
{
NULL,
};

/* UART Driver Parameters */
UART_Params gUartParams[CONFIG_UART_NUM_INSTANCES] =
{
{
.baudRate = 115200,
.dataLength = UART_LEN_8,
.stopBits = UART_STOPBITS_1,
.parityType = UART_PARITY_NONE,
.readMode = UART_TRANSFER_MODE_BLOCKING,
.readReturnMode = UART_READ_RETURN_MODE_FULL,
.writeMode = UART_TRANSFER_MODE_BLOCKING,
.readCallbackFxn = NULL,
.writeCallbackFxn = NULL,
.hwFlowControl = FALSE,
.hwFlowControlThr = UART_RXTRIGLVL_16,
.transferMode = UART_CONFIG_MODE_INTERRUPT,
.skipIntrReg = FALSE,
.uartDmaIndex = -1,
.intrNum = 38U,
.intrPriority = 4U,
.operMode = UART_OPER_MODE_16X,
.rxTrigLvl = UART_RXTRIGLVL_8,
.txTrigLvl = UART_TXTRIGLVL_32,
.rxEvtNum = 0U,
.txEvtNum = 0U,
},
};

void Drivers_uartOpen(void)
{
uint32_t instCnt;
int32_t status = SystemP_SUCCESS;

for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
{
gUartHandle[instCnt] = NULL; /* Init to NULL so that we can exit gracefully */
}

/* Open all instances */
for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
{
gUartHandle[instCnt] = UART_open(instCnt, &gUartParams[instCnt]);
if(NULL == gUartHandle[instCnt])
{
DebugP_logError("UART open failed for instance %d !!!\r\n", instCnt);
status = SystemP_FAILURE;
break;
}
}

if(SystemP_FAILURE == status)
{
Drivers_uartClose(); /* Exit gracefully */
}

return;
}

void Drivers_uartClose(void)
{
uint32_t instCnt;

/* Close all instances that are open */
for(instCnt = 0U; instCnt < CONFIG_UART_NUM_INSTANCES; instCnt++)
{
if(gUartHandle[instCnt] != NULL)
{
UART_close(gUartHandle[instCnt]);
gUartHandle[instCnt] = NULL;
}
}

return;
}

This is main code for reading the adc register value and printing.

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/*
 *  Copyright (C) 2022-2023 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

/*
 *  Copyright (C) 2022-2023 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include <kernel/dpl/ClockP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/epwm.h>
#include <drivers/adc.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"


/*
 * Example Description :
 *      This examples demonstrates periodical triggering of conversion on ADC1
 * by EPWM0
 *
 * SOC Configurations :
 * - SOC 0 trigger is set by EPWM0SOCA
 * - Samples on ADC1 Channel 0
 *
 * Interrupt Configurations :
 * - ADC1INT1 source is set to EOC/SOC0
 * - INTXBAR0 is set to ADC1INT1.
 *
 * ISR App_adcISR
 * - reads the SOC0 result.
 *
 * External Connections :
 * - CC:
 *     feed analog input on ADC 1 Channel 0 - HSEC connecter pin - 12
 * - LP:
 *     feed analog input on ADC 1 Channel 0 - J1/J3 Pin - 24
 *
 * Watch Variables :
 * - gAdc1Result0 : the array holds the sampled values of the ADC 1 Channel 0
 */


/* Number of ADC conversions required */
#define ADC_CONVERSION_COUNT    400

/* Global variables and objects */
volatile uint32_t gAdc1Result0[ADC_CONVERSION_COUNT];
volatile uint32_t gIndex = 0;

uint32_t gAdc1baseAddr = CONFIG_ADC1_BASE_ADDR;
uint32_t gAdc1resultBaseAddr = CONFIG_ADC1_RESULT_BASE_ADDR;

static HwiP_Object  gAdcHwiObject;

/* Variable to store the count of completed conversions
Initialising conversion count to 0 */
volatile uint32_t gAdcConversionCount = 0;

static void App_adcISR(void *args);

void adc_soc_epwm_main(void *args)
{


    /* Open drivers to open the UART driver for console */
    Drivers_open();
    Board_driversOpen();

    DebugP_log("ADC Soc EPWM Test Started\r\n");

    int32_t  status;
    /* Initialising a Interrupt parameter */
    HwiP_Params  hwiPrms;
    /* Register & enable interrupt */
    HwiP_Params_init(&hwiPrms);
    hwiPrms.intNum      = CSLR_R5FSS0_CORE0_CONTROLSS_INTRXBAR0_OUT_0;
    hwiPrms.priority    = 0;                        /* setting high priority. optional */
    hwiPrms.callback    = &App_adcISR;
    status              = HwiP_construct(&gAdcHwiObject, &hwiPrms);
    DebugP_assert(status == SystemP_SUCCESS);

    /* Starting the EPWM-TB Counter*/
    EPWM_setTimeBaseCounterMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_MODE_UP);

    /* Wait until all the conversions are done.*/
    while (gAdcConversionCount < ADC_CONVERSION_COUNT);

    DebugP_log("ADC1 SOC0 results\r\n");
    for(int iter = 0; iter < gIndex; iter+= 1)
    {
        DebugP_log("\t%d\r\n",gAdc1Result0[iter]);
    }

    DebugP_log("ADC Soc EPWM Test Passed\r\n");
    DebugP_log("All tests have passed!!\r\n");

    Board_driversClose();
    Drivers_close();
}

static void App_adcISR(void *args)
{
//    printf("inside the printf \n");

    if (gAdcConversionCount < ADC_CONVERSION_COUNT)
    {
        ADC_clearInterruptStatus(gAdc1baseAddr, ADC_INT_NUMBER1);
        gAdc1Result0[gIndex] = ADC_readResult(gAdc1resultBaseAddr, ADC_SOC_NUMBER0);
        gIndex++;
        gAdcConversionCount++;

//        printf("%d \n",gAdc1Result0[gIndex]);
    }
    else
    {
        /* stopping the TBCounter to halt PWM*/
        EPWM_setTimeBaseCounterMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_MODE_STOP_FREEZE);
    }
    ADC_clearInterruptStatus(gAdc1baseAddr, ADC_INT_NUMBER1);
    if(true == ADC_getInterruptOverflowStatus(gAdc1baseAddr, ADC_INT_NUMBER1))
    {
        ADC_clearInterruptStatus(gAdc1baseAddr, ADC_INT_NUMBER1);
        ADC_clearInterruptOverflowStatus(gAdc1baseAddr, ADC_INT_NUMBER1);
    }
}

pls tell where i am getting wrong?

0 Fleenor 11 months ago in reply to Tej_1441

TI__Mastermind 20212 points

Hello Tej_1441,

Is it possible to insert some kind of voltage buffer on the input? Can you share the specs of the signal generator you are using? I don't see any issue with your code, but believe the issue could be related to the drive strength of your instrument.

Best Regards,

Zackary Fleenor

0 Tej_1441 11 months ago in reply to Fleenor

Prodigy 160 points

Hii Fleenor,
It is not possible to insert voltage buffer.
I am using Tektronix signal generator with model number AFG31000 SERIES Arbitrary function generator.
https://www.tek.com/en/datasheet/arbitrary-function-generators

Here i have attached the image of plotted graph for constant amplitude( amplitude = 0.5v and offset = 0.250v) and different frequency for ADC conversion.
Sampling rate is set to 4MSPS and frequency for triggering SOC from epwm is set to be 1MHz.

why on increasing frequency, range of value captured by ADC is decreasing.
And i am receiving 50 sample at 20KHz which means sampling rate=1msps ( Is sampling rate effected by frequency by which we trigger adc SOC)

graph at 5KHz

graph at 10 KHz

graph at 20 KHz

graph at 50KHz

Graph at 100KHz

Graph at 200KHz

graph at 400KHz

0 Fleenor 11 months ago in reply to Tej_1441

TI__Mastermind 20212 points

Hey Tej_1441,

I spoke with the design engineer here and came up with the following feedback.

1) It looks like a low-pass filter in the HW is acting upon the signal. Can you check the board for any possible LPF elements?

2) If the EPWM SoC Trigger is set to 1MHz, then you are only generating data at 1MSPS. (The EPWM trigger rate is directly related to the sampling rate).

3) Can you also please provide captures of the input waveform? The "InstaView" technology of the Function Generator you are using seems promising to provide some additional clues.

Best Regards,

Zackary Fleenor

0 Tej_1441 11 months ago in reply to Fleenor

Prodigy 160 points

Hii Fleenor,
I am using sitara AM263x MCU with PART NO : LP-AM263.
1 ) I have checked the HW, but there is no LPF elements.
2 ) It can be noticed from the images in previous reply that number of sample for 1MHz is correct ( trigger for ADC's SOC is set to 1MHz), But the problem is that signal is not getting uniformly sampled.

Here i am attaching the captures of input waveform

Here are details obtained from the "InstaView" technology of Function Generator.

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DHCP    On
CLOCK_REFERENCE Internal
GPIB_ADDRESS    1.10000000000000000000e+01
GPIB_CONFIGURATION  Talk/Listen
LANGUAGE    English
SCREEN_SAVER    Off
CONTRAST    7.00000000000000000000e+01
CLICK_TONE  On
SOFT_KEYBOARD   On
BEEPER  On
POWER_ON    Default
BRIGHTNESS  1.00000000000000000000e+02
TRIGGER_SOURCE  External
TRIGGER_SLOPE   Positive
TRIGGER_INTERVAL    1.00000000000000002082e-03
TRIGGER_OUT Trigger
TIMEZONE    UTC+08:00
USB_ESER    0.00000000000000000000e+00
USB_SRER    0.00000000000000000000e+00
USB_QEN 0.00000000000000000000e+00
USB_OEN 0.00000000000000000000e+00
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

DHCP	On
CLOCK_REFERENCE	Internal
GPIB_ADDRESS	1.10000000000000000000e+01
GPIB_CONFIGURATION	Talk/Listen
LANGUAGE	English
SCREEN_SAVER	Off
CONTRAST	7.00000000000000000000e+01
CLICK_TONE	On
SOFT_KEYBOARD	On
BEEPER	On
POWER_ON	Default
BRIGHTNESS	1.00000000000000000000e+02
TRIGGER_SOURCE	External
TRIGGER_SLOPE	Positive
TRIGGER_INTERVAL	1.00000000000000002082e-03
TRIGGER_OUT	Trigger
TIMEZONE	UTC+08:00
USB_ESER	0.00000000000000000000e+00
USB_SRER	0.00000000000000000000e+00
USB_QEN	0.00000000000000000000e+00
USB_OEN	0.00000000000000000000e+00
USB_PSC	On
GPIB_ESER	0.00000000000000000000e+00
GPIB_SRER	0.00000000000000000000e+00
GPIB_QEN	0.00000000000000000000e+00
GPIB_OEN	0.00000000000000000000e+00
GPIB_PSC	On
VXI11_ESER	0.00000000000000000000e+00
VXI11_SRER	0.00000000000000000000e+00
VXI11_QEN	0.00000000000000000000e+00
VXI11_OEN	0.00000000000000000000e+00
VXI11_PSC	On
BURST_COUNT1	5.00000000000000000000e+00
BURST_MODE1	Triggered
FREQUENCY_CONCURRENT1	Off
FUNCTION1	Sine
FUNCTION_FILE1	""
VOLTAGE_CONCURRENT1	Off
LOAD_IMPEDANCE1	5.00000000000000000000e+01
AMPLITUDE_UNIT1	Vpp
AMPLITUDE_VPP1	5.00000000000000000000e-01
AMPLITUDE_VRMS1	1.76776695296636865429e-01
AMPLITUDE_DBM1	-2.04119982655924836479e+00
OFFSET1	2.50000000000000000000e-01
HIGH_LEVEL1	5.00000000000000000000e-01
LOW_LEVEL1	0.00000000000000000000e+00
AMPLITUDE_OR_LEVEL1	Amplitude
HIGH_LIMIT1	2.50000000000000000000e+00
LOW_LIMIT1	-2.50000000000000000000e+00
INVERT1	Off
NOISE_ADD1	Off
NOISE_LEVEL1	1.00000000000000000000e+01
EXTERNAL_ADD1	Off
PULSE_WIDTH1	5.00000000000000040902e-06
PULSE_DUTY1	5.00000000000000000000e+01
PULSE_WIDTH_OR_DUTY1	Duty
PULSE_LEADING_EDGE1	2.00000000000000012456e-09
PULSE_TRAILING_EDGE1	2.00000000000000012456e-09
RAMP_SYMMETRY1	5.00000000000000000000e+01
NOISE_SIGMA1	2.00000000000000011102e-01
FREQUENCY1	1.00000000000000000000e+05
PERIOD1	1.00000000000000008180e-05
FREQUENCY_OR_PERIOD1	Frequency
PHASE1	0.00000000000000000000e+00
LEAD_DELAY1	0.00000000000000000000e+00
PHASE_CONCURRENT1	Off
RUN_MODE1	Continuous
MODULATION_TYPE1	AM
AM_SOURCE1	Internal
AM_SHAPE1	Sine
AM_SHAPE_FILE1	""
AM_FREQUENCY1	1.00000000000000000000e+04
AM_DEPTH1	5.00000000000000000000e+01
FM_SOURCE1	Internal
FM_SHAPE1	Sine
FM_SHAPE_FILE1	""
FM_FREQUENCY1	1.00000000000000000000e+04
FM_DEVIATION1	1.00000000000000000000e+06
PM_SOURCE1	Internal
PM_SHAPE1	Sine
PM_SHAPE_FILE1	""
PM_FREQUENCY1	1.00000000000000000000e+04
PM_DEVIATION1	9.00000000000000000000e+01
PWM_SOURCE1	Internal
PWM_SHAPE1	Sine
PWM_SHAPE_FILE1	""
PWM_FREQUENCY1	1.00000000000000000000e+04
PWM_DEVIATION1	5.00000000000000000000e+00
FSK_SOURCE1	Internal
FSK_RATE1	5.00000000000000000000e+01
FSK_HOP_FREQUENCY1	1.00000000000000000000e+06
SWEEP_START1	1.00000000000000000000e+05
SWEEP_STOP1	1.00000000000000000000e+06
SWEEP_CENTER1	5.50000000000000000000e+05
SWEEP_SPAN1	9.00000000000000000000e+05
SWEEP_START_STOP_OR_CENTER_SPAN1	StartStop
SWEEP_TIME1	1.00000000000000002082e-02
SWEEP_RETURN_TIME1	1.00000000000000002082e-03
SWEEP_HOLD_TIME1	0.00000000000000000000e+00
SWEEP_TYPE1	Linear
SWEEP_MODE1	Repeat
BURST_DELAY1	0.00000000000000000000e+00
BURST_IDLE_STATE1	StartPoint
RTWM_CABLE_DELAY1	5.23999999999999927584e-09
BURST_COUNT2	5.00000000000000000000e+00
BURST_MODE2	Triggered
FREQUENCY_CONCURRENT2	Off
FUNCTION2	Sine
FUNCTION_FILE2	""
VOLTAGE_CONCURRENT2	Off
LOAD_IMPEDANCE2	5.00000000000000000000e+01
AMPLITUDE_UNIT2	Vpp
AMPLITUDE_VPP2	1.00000000000000000000e+00
AMPLITUDE_VRMS2	3.53553390593273730858e-01
AMPLITUDE_DBM2	3.97940008672037537352e+00
OFFSET2	0.00000000000000000000e+00
HIGH_LEVEL2	5.00000000000000000000e-01
LOW_LEVEL2	-5.00000000000000000000e-01
AMPLITUDE_OR_LEVEL2	Amplitude
HIGH_LIMIT2	2.50000000000000000000e+00
LOW_LIMIT2	-2.50000000000000000000e+00
INVERT2	Off
NOISE_ADD2	Off
NOISE_LEVEL2	1.00000000000000000000e+01
PULSE_WIDTH2	4.99999999999999977374e-07
PULSE_DUTY2	5.00000000000000000000e+01
PULSE_WIDTH_OR_DUTY2	Duty
PULSE_LEADING_EDGE2	2.00000000000000012456e-09
PULSE_TRAILING_EDGE2	2.00000000000000012456e-09
RAMP_SYMMETRY2	5.00000000000000000000e+01
NOISE_SIGMA2	2.00000000000000011102e-01
FREQUENCY2	1.00000000000000000000e+06
PERIOD2	9.99999999999999954748e-07
FREQUENCY_OR_PERIOD2	Frequency
PHASE2	0.00000000000000000000e+00
LEAD_DELAY2	0.00000000000000000000e+00
PHASE_CONCURRENT2	Off
RUN_MODE2	Continuous
MODULATION_TYPE2	AM
AM_SOURCE2	Internal
AM_SHAPE2	Sine
AM_SHAPE_FILE2	""
AM_FREQUENCY2	1.00000000000000000000e+04
AM_DEPTH2	5.00000000000000000000e+01
FM_SOURCE2	Internal
FM_SHAPE2	Sine
FM_SHAPE_FILE2	""
FM_FREQUENCY2	1.00000000000000000000e+04
FM_DEVIATION2	1.00000000000000000000e+06
PM_SOURCE2	Internal
PM_SHAPE2	Sine
PM_SHAPE_FILE2	""
PM_FREQUENCY2	1.00000000000000000000e+04
PM_DEVIATION2	9.00000000000000000000e+01
PWM_SOURCE2	Internal
PWM_SHAPE2	Sine
PWM_SHAPE_FILE2	""
PWM_FREQUENCY2	1.00000000000000000000e+04
PWM_DEVIATION2	5.00000000000000000000e+00
FSK_SOURCE2	Internal
FSK_RATE2	5.00000000000000000000e+01
FSK_HOP_FREQUENCY2	1.00000000000000000000e+06
SWEEP_START2	1.00000000000000000000e+05
SWEEP_STOP2	1.00000000000000000000e+06
SWEEP_CENTER2	5.50000000000000000000e+05
SWEEP_SPAN2	9.00000000000000000000e+05
SWEEP_START_STOP_OR_CENTER_SPAN2	StartStop
SWEEP_TIME2	1.00000000000000002082e-02
SWEEP_RETURN_TIME2	1.00000000000000002082e-03
SWEEP_HOLD_TIME2	0.00000000000000000000e+00
SWEEP_TYPE2	Linear
SWEEP_MODE2	Repeat
BURST_DELAY2	0.00000000000000000000e+00
BURST_IDLE_STATE2	StartPoint
RTWM_CABLE_DELAY2	0.00000000000000000000e+00

Pls once verify the example code adc_soc_epwm (ti.com) is woking correctly.

+1 Fleenor 11 months ago in reply to Tej_1441

TI__Mastermind 20212 points

Hello,

The example code is working as expected.

The AM263x Launchpad has 0.1µF capacitor to ground at the ADCx_AINy boosterpack pin. This is parallel to the load applied by the function generator and results in a LPF response that is likely attenuating signals in the 100KHz range as shown.

Best Regards,

Zackary Fleenor

0 Tej_1441 11 months ago in reply to Fleenor

Prodigy 160 points

Hii Fleenor,
Thanks a lot for your help! Your suggestion to remove 0.1uF capacitor fixed the issue I was having.
I really appreciate you for giving your time.

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