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Hi,
I'm starting a new project that uses different peripherals, including the ADC. I'm using the adc12_sequence_conversion example. I'm a bit confused about setting the timing of the sampling window and the conversion window using syscfg.
I've attached two images: Timing diagram block and syscfg of the adc12_sequence_conversion example.
1 - Regarding the sampling window: Where do I set the value of the sampling window using .syscfg?
2 - Regarding the conversion window: how do I determine this period? I know it is defined by RES and CLKFREQ (described in the diagram), but is there an equation or reference to estimate it? How are they related?
3 - What is the sampling window in the example?
Translated with DeepL.com (free version)
Thank you for the support.
Hi Adelson,
The sampling window is set in sysconfig under "Advanced Configuration." Look for the Desired Sample Time 1 and Desired Sample Time 0 fields:
Please note that you select which of these two values to use for a given channel in the "ADC Memory Conversion x Configuration" section.
The conversion window is based on your resolution, and the 80MHz conversion clock included in the ADC (See TRM for number of clock cycles).
So in 12-bit mode the conversion phase would take 14 cycles/80Mhz, or ~175ns.
Best Regards,
Brandon Fisher
Hi Adelson,
The sample window is defined by the sampling time under the advanced configuration section in the ADC module of SysConfig. The code that SysConfig generates will be changing the SCOMP register.
The conversion cycles are always a static number based on your resolution, the timing will be based on your source clock.
Regards,
Luke
Hi Brandon and Luke,
Thanks for the prompt feedback.
Then, two more questions.
1) if I want to work with the highest sample rate (4MS/s), could the following configuration be an option?
MLCK = 80 MHz (Fig 1)
UPCLK = ADCCLK Frequency Range (MHz) = 40 MHz; (Fig 2 - clkconfig)
Resolution = 12-bit -> 8 clock cycles; (Fig 3 - clockrange)
Sampling time = 50ns (Fig 2 - clkconfig)
Calculated conversion frequency = 4 MHz. (Fig 2 - clkconfig)
2) The total clock cycles in AUTO-MODE (Fig 10.2 - previous answer):
*Considering ULPCLK as the source for ADCCLK, so Sync_cycles = 0.
Total cycles = Sync_cycles * + sampling window + conversion window + written to MEMRESx
Total cycles = 0 + 2 + (8) + 1 = 11 cycles;
Does this calculation make sense? The conversion window for 12 bit is 14 or 8 cycles?
Fig. 1
Fig. 2
FIg. 3
Thank you very much for your support
Hi Adelson,
We have an example that will give you the max sampling rate -> adc12_max_freq_dma_LP_MSPM0G3507
This device's ADC has an internal conversion clk which is why you will have a static 14, 12, or 9 conversion clock cycles.
For the minimum sampling time, the datasheet spec is 62.5 ns
Regards,
Luke
