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MSPM0L1106: SPI buffer behavior

Guillaume Henri
Expert 3896 points
Part Number: MSPM0L1106

Hi MSPM0 champs,

We would have specific questions about the SPI module behavior on MSPM0L11xx :

Q1/ When sending 8-bit data to the SPI Tx buffer, is the response stored in the Rx buffer?

Q2/ What happens if the received response is not read before the next transmission? Will it overwrite the existing data or be stored in another available location?

Thank you!

Best regards,

Guillaume

  • 0
    Guru 38390 points

    Q1: No, TX and RX are independent.

    Q2: There is no RX buffer Buffer. As soon as the next SPI is received, it overwrites the buffer.

  • 0
    Guru 38390 points

    I spoke too soon, there is a 4 byte FIFO you can activate to provide both a TX and RX buffer buffer.

  • 0
    TI__Mastermind 27560 points

    Hey Guillaume,

    So for SPI mode, we can be either the Controller or the Peripheral unit and the role really just determines which side controls the clock.  Regardless of the role, when 8 clocks are on the SPI bus, the 8-bits in the TX buffer are transmitted out and simultaneously 8 bits are are clocked into the RX buffer. 

    As Keith mentioned, there is a 4 byte RX FIFO that can be configured on this device, but if it's not service, then the data will be lost.  

    Do that address your question?  I feel like you're asking about a specific circumstance but I didn't understand exactly what it was.  

    Thanks,

    JD