MSPM0G1107: "Failsafe" SW implementation of PWM signal

Hi Jose,

Can an external pull down resistor help in your application?

Best regards,

Cash Hao

Hello,

There is already a pull-down resistor, but it will not be enough for this function.

The question is more related with definition of pin direction (in/out) and state (low/high) during and after a reset condition in the MCU. The pull-down resistor only works when the pin is not defined as "output low".

Thank you.

Hi,

Okay, get it. 

My thought is that setting the PA7 as the BSL invoke pin. Since you have a pull down resistor, you do not need to concern about going into BSL mode. I think it could help to control the PA7 status during the reset procedure. 

Best regards,

Cash Hao

Ok, agree.

What is the right procedure to assure that this pin will be used only as "output low" when PWM duty cycle is set to zero?

And to assure this configuration in all operating modes (e.g. power supply turn ON, reset from NRST, reset from watchdog, reset from SW instruction, etc...)?

Thank you.

Hi,

If you use the pin that only have digital function no mux with analogy function like ADC, OPA, COMP, crystal and etc. During the reset procedure, these pin will be set as High-Z and the status will depends on the external circuit. 

For those pin mux with analogy function, you might not able control its status during the reset process. 

Best regards,

Cash Hao 

Hello,

The pin in this case is PA7, using timer G7. A pull-down resistor is assembled for setting the default electrical state for this pin.

Therefore, if the pin is "high" just before any reset action/source, will it switch to "High-Z" during the next microseconds, until the pin is initialized again?

Or will it remain in "high" state until code reaches the initialization functions? If this is the case, for how long?

Thank you!

Hi,

It will switch to "High-Z" until the pin is initialized again. Because during the reset, the DOE and DOUT register will be set to zero, and make the pin shows as "HIgh-Z". 

Best regards,

Cash Hao

Hello,

Thank you very much for the confirmation.

I only have a final doubt/question regarding this topic: what is exactly the contribution of "t(start) RESET" during this reboot process? Will it be neutral or we can expect that PA7 will remain "high" during this period, before switching to "High-Z" ?

Hi,

This time is how long does the MCU boot code cost. It is usually from release on RST pin from low status or supply VDD to MCU to MCU runs into the first  application code. 

The DOE and DOUT register should be cleared as zeros before you release the RST pin from low. The PAx status should be High-Z in this situation. 

Best regards,

Cash Hao

Hello,

This is the type of feedback I was looking for. We will perform additional tests on our side and try to validate your feedback.

Thank you again.

Hi,

Okay, wait for your feedbacks. 

Best regards,

Cash Hao

Hello,

Please check the example in the following figure:

Channel 1: PA7 (PWM)

Channel 2: Reset line of the MCU (pulled low manually with a switch)

Channel 4: PA4 (GPIO that is always '1' after initialization by the software).

During several actions on the switch that resets the MCU, there is always a latency of approx. 250 us, when measured from the falling edge of the reset line to the falling edge of PA7/PA4.

What is the possible explanation for this behaviour and what could be the solution (by software only) to assure that PA7 is low after the falling edge of the reset line?

Thank you!

Hi,

Okay. I see. 

The 250us should be take for the MCU to clear DOE and DOUT register after it receive the RST signal. 

I do not think of a way to avoid this only on the software side. On the hardware side, a AND gate circuit of the PAx and RST pin should solve this issue. 

Best regards,

Cash Hao