Tool/software:
2 out of 11 boards (custom application boards for FW development) had the same failure on MSPM01507, just after a few hours of usage.
TI has started an FA on the 2 MSP's removed from the board, and they both tested with VSS to VDD short (or low resistance) and all other pins tested normal.
In our application, we power down the MSP for system shutdown mode, and the MSP 3.3V rail goes to zero. In our test environment, when we wake up the MCU by enabling the 3.3V rail, we might have an illegal condition where an MSP input pin biased by a 3.3V output from our UART driver (Tx of our tester, driving Rx of the MSP) to around 3.3V. In this condition, the 3.3V rail is driven by forward biased ESD diode at the MSP input pin being driven high. The 3.3V rail under this condition is about 2.7v, which makes sense, as we have a forward biased ESD diode at 0.6V. My question is this: If the VDD/VSS damage mechanism is SCR latch-up, resulting from our illegal condition during MSP power up, should the VDD/VSS damage area be around the GPIO that has the illegal logic 1 during the power on event?
Are there any TI documents for MSP interfaces, that warn against having an input driven logic 1, before and during the time the power rail is enabled?
