MSPM0L2228: SYSOSC frequency calibration

24 MHz trim using FCC_32.768kHz calibration_VSSOP28(1).zip

Here is a code to use LFCLK to trim SYSOSC. You can ask your customer refer to that.

Hi Eason,

Thanks for the project. It seems the code calibrates SYSOSC to 24MHz.
The customer's target frequency is 32MHz.
Is the project usable for target frequency = 32MHz?
I guess the below procedure is used in the code, but it seems targets are 16MHz or 24MHz.



Thanks and regards,
Koichiro Tashiro

Yes. You are right. It is for 16MHz or 24MHz. Can you check with customer if this 24MHz or 16MHz is OK?

Hi Eason,

Eason Zhou said:

Can you check with customer if this 24MHz or 16MHz is OK?

Unfortunately, the customer needs 32MHz.
So there is no solution?

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

I will reply to you about this issue tomorrow morning.

Best Regards,

Janz Bai

Hello Koichiro,

You can find the "Chapter 2.3.1.2.4 SYSOSC User Trim Procedure" in our TRM. 

In fact, the CAP, RESCOARSE, RESFINE and RDIV controls the modification of SYSOSC frequency. So I recommend:

1. Modify the SYSOSC frequency manually

1). Using the CLK_OUT to measure current SYSOSC frequency;

2). Increasing / decreasing the RESFINE / RDIV according to current SYSOSC frequency (if FCL disable -> modify the RESFIN, if FCL enable -> modify the RDIV);

3). Run the modified code and measure the CLK_OUT, then continue to increase / decrease the RESFINE/ RDIV value to close the value you want;

2. Modify the SYSOSC frequency automatically

1). Using FCC to calculate the current SYSOSC frequency value, not to measure the CLK_OUT manually every time;

2). The basic code logic can refer to the code Eason sent to you but you need to do some modification;

Notice: 

1). set the RESFINE / RDIV to mid-range when you start to do trim, can't begin at 0x0;

2). Remember not to set the SYSOSC frequency too larger than 32 MHz which will make MCU error (can't be connected and need to be factory reset).

Best Regards,

Janz Bai

Hi Janz,

Thanks for your reply.

Janz Bai said:

You can find the "Chapter 2.3.1.2.4 SYSOSC User Trim Procedure" in our TRM. 

Even the description says "The SYSOSC can be trimmed to a user-trimmed value of 16MHz or 24MHz, if desired.", it can be officially supported to use for 32MHz?
If so, please update TRM.

In the trimming sequence, there are a few parts which are 16MHz or 24MHz specific.
- SYSOSCTRIMUSER.FREQ value is only for 16MHz or 24MHz. Which value is used for 32MHz?
- It is not clear what is CAP field value for 32MHz.

Thanks and regards,
Koichiro Tashiro

Hello Koichiro,

Sorry for the late reply. I will summary some important points tomorrow here and send an email to our design team for some details tomorrow too.

Best Regards,

Janz Bai

Hello Koichiro,

I have spent some time to check my code and related description in our TRM. Now customer have achieved the 0.53%, which is about 169 kHz by using FCL. It seems that using the RDIV (50 kHz step) can achieve 0.16 % according to the "Trim procedure using CLK_OUT with frequency correction loop (FCL) enabled (ROSC resistor present)". So the core point is how to calibrate the SYSOSC when FCL is disable according to the "Trim procedure using CLK_OUT with frequency correction loop (FCL) disabled (No ROSC resistor)" before enabling the FCL. In other words, the core point is:

1). How to set the SYSOSCCFG register and how to set the Cap in the SYSOSCTRIMUSER register in "Trim procedure using CLK_OUT with frequency correction loop (FCL) enabled (ROSC resistor present)"

2). How to set the SYSOSCCFG register in the "Trim procedure using CLK_OUT with frequency correction loop (FCL) disabled (No ROSC resistor)"

About this question, I have sent email to design team and after these questions have been confirmed, I will tie the response here as soon as possible.

Best Regards,

Janz Bai

Hi Janz,

Thanks for your reply. I understood there is no way to calibrate 32MHz SYSOSC.

Thanks and regards,
Koichiro Tashiro