• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 31 subscribers
  • Views 182 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSPM0G3507: SPI chip select control in DMA mode

Mykola Zaitsev
Prodigy 60 points
Part Number: MSPM0G3507

Tool/software:

Hello,

I am using spi driver in DMA mode (as in the sdk example) and I see that chip select line is asserted before and de-asserted after each byte of multi byte data transfer. Is it possible to configure it in a way that it is asserted ones in the beginning of a multi byte transfer and de-asserted at the end of the transfer?

I know that it is possible to use spi in the 3 wire mode and do it manually, but curious if there is a cleaner solution.

Kind regards,

Mykola

  • +1
    Guru 95280 points

    Short answer: No.

    Longer answer: TRM (SLAU846A) Sec 17.2.3 makes reference to "continuous back-to-back" transfers, during which /CS is kept low. In context (and by comparison with e.g. the Tiva TRM) this means "as long as the Tx shift register never goes empty". This means that your transaction may be truncated if you're a bit late. I (personally) consider this a fragile premise. The reliable method is to do /CS as a GPIO.

    That said, I'm a bit surprised that the DMA doesn't (usually) maintain a "continuous back-to-back" transfer. But even the DMA can't guarantee it.

  • 0 in reply to Bruce McKenney
    Prodigy 60 points

    Thank you for the feedback. I appreciate it.