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Tool/software:
Hi expert
i use "spi_controller_fifo_dma_interrupts_LP_MSPM0G3507_nortos_ticlang" as base to write a spi eeprom read/write module,
and i got a confusing behavior in receive, the symptom is "i can't get fixed address in RxPacket data array in every receive"
please see my step describe as below
// step1
send a write command and breakpoint in line 71(main), the command send correct and LA get correct dataflow(P1)
// step2
send a read command and breakpoint in line 75(main), get response data in NO.7 and NO.8 of gRxPacket array(P2)
i think the dataflow in LA is normal(P2_LA) but why data not appear in in NO.0 and NO.1 of gRxPacket?
// step3
send a read command again and breakpoint in line 79(main), get response data in NO.4 and NO.5 of gRxPacket array(P3)
the dataflow in LA is normal(P3_LA) but why the data appear in in NO.4 and NO.5 of gRxPacket in this time?
in my opinion i thinks i should get data in NO.0 and NO.1 of gRxPacket every time, because i run the same read subroutine
but that doesn't seem to be the case.
i offer my project file, please help me to check my problem.
I'm beyond grateful.
The SPI is intrinsically bi-directional. For every Tx byte sent, there is a corresponding Rx byte received. This is the case even if you're not interested in the Rx byte.
Your eeprom_write function sends some number of bytes, so it will result in that many (max 4) bytes in the Rx FIFO. Those will stay there until your code (or the DMA) reads them out, and thus they will be the first bytes you read in the subsequent eeprom_read call.
There are two tactics to deal with this:
1) Run the Rx DMA channel every time you do a "Tx only" transaction (use the same length), then ignore what was read into gRxPacket
or
2) After each "Tx only" transaction (don't forget the WREN transaction), empty the Rx FIFO by just reading and throwing away the bytes.
Hi Bruce
thanks for your help, i use tactics 1 and i can get fixed response data in gRxPacket
thanks again.