[FAQ] AM2634: Board bring-up FAQ for custom AM263x/AM263Px PCB systems

1. Hardware and Power Checks
   1. Verify proper power sequencing on the AM26x device:
      • There is no sequencing requirement with respect to the primary core digital VDD 1.2V and I/O power 3.3V rails.
      • There are two on-die LDO that are supplied through the VDDS33 and VDDA33 power nets respectively. These on-die LDO generate the required VDDS1V8 and VDDA1V8 1.8V digital and analog power. The AM263Px does require the minimum ramp time be respected for 3.3V power-on.
      • Additional PORz and SOP boot mode latch timing must be respected by the PCB system design
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   2. Verify proper voltage levels on AM26x device power rails by probing test points
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   3. Verify that max current loading is not being exceeded
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   4. For specific power topology references, see the AM26x Hardware Design Guidelines document
      • Discrete DC-DC Power Solution: Section 2.1
      • Integrated PMIC Power Solution: Section 2.2
2. If power rail checks are nominal, move on to checking the device boot status.
   1. Verify proper pulls on device SOP[3:0] pins. SOP[3:0] must be connected to the corresponding power supply or ground (VSS) through separate external pull resistors to ensure these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode.
      • AM26x SOP Pin assignments:
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      • AM26x Boot Modes:
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      • AM26x Boot Mode SOP configuration:
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      • NOTE: OSPI Boot Mode is only supported on AM263Px devices. AM263x devices do not support OSPI Boot Mode. 
   2. Verify proper SOP boot mode latch timing
      • Refer to the timing diagram in 1.a of this FAQ: 
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      • The SOP pins are latched in the internal circuit on the SoC when the device Power Management Unit provides a VDD_OK signal
        • VDD_OK is generated once all device supplies have ramped up and are stable. The critical supply that ramps last and triggers VDD_OK is the Analog 1V8 supply - VDDA18
        • VDDA18 ramps once PORz is released
      • The critical sequence to note is: PORz goes high -> 1V8 Analog LDO Supply ramps (VDDA18) -> VDD_OK signal is triggered, SOP pin states are sampled
        
        • There is no explicit pin signal available to probe to indicate when the SOP pin states are sampled to latch the boot mode. Theoretically, one can monitor the 1V8 Analog LDO ramp on a VDDA18 pin to find this point
        • After the VDD_OK signal is triggered, the AM26x device boots for 2-6ms
        • The last point of boot is the WARMRSTn release. This is the last point after which SOP pins are not necessary to hold their states and can be changed.
   3. Verify correct SOP pin isolation from functional pin modes
      • Because of the SOP/functional-mode multiplexing on AM26x devices, additional care must be taken in schematic and layout to ensure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP mode branches do not present inductive stubs to the functional mode signal paths. Failing to take care of this may result in non-functional OSPI/QSPI or SPI interfaces.
      • SOP mode isolation is accomplished by including a 10KΩresistor in the SOP signal path. The resistor is placed such as one pad is as close to the AM26x BGA pad and in-line with the functional mode path. This creates a layout where the additional stub length necessary to breakout the SOP pathwill only minimally impact the functional mode operation of the signals
      • Reference: https://www.ti.com/lit/an/sprabj8b/sprabj8b.pdf, Section 5.1
3. If the device boot status is verified and functional, next check the device UART output to verify that the device boots and is alive.
   1. Set the AM26x device boot mode to UART Boot Mode by setting the SOP[3:0] pins to 0001
      • Boot Mode with UART Fallback (such as QSPI 4S mode) can also be set. Refer to the Boot Mode table in section 2.a of this FAQ.
   2. Connect device UART0 RX/TX pins to host PC/terminal using XDS110 or similar hardware debugger
   3. On Windows, use the Device Manager application to check that UART ports are being detected
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   4. Open UART terminal application, such as Tera Term
   5. In Setup -> Serial Port, configure the following settings:
      • Port: COM### (Class Application/User UART)
      • Speed: 115200
      • Data: 8 bit
      • Parity: none
      • Stop bits: 1 bit
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   6. Assert PORz (Power-On-Reset) on the device - can be accomplished by power cycling device, or triggering reset circuit on custom PCB
   7. Confirm ASCII character 'C' is bring printed to the UART console
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   8. If C's are not being printed to console:
      • Check that baud rate = 115200
      • Confirm boot mode is UART (or boot mode with UART fallback)
      • Power-on-reset device
      • UART Console after Power-On-Reset, with 'C's printing at the end of the UART output
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4. If the device UART output is verified, the device is alive on the PCB. Next, verify the device JTAG connection
   
   1. Connect device JTAG pins to host PC using XDS110 or similar hardware debugger
   2. Confirm AM26x device bootmode is set to DevBoot - SOP[3:0] = 1011
   3. Ensure you have the latest version of Code Composer Studio downloaded - https://www.ti.com/tool/CCSTUDIO
      • If downloading for the first time, select Custom Installation in the installer
      • Select Sitara AM2x MCUs when selecting components
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   4. Create new target connection for AM26x device
      • In CCS: View -> Target Configurations
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      • In the Target Configurations tab: User Defined -> New Target Configuration
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      • Name the Target Configuration and click Finish
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      • In General Setup, select the Connection (XDS110 USB Debug Probe in this example) and AM26x device being used on the PCB system (AM263Px used as an example)
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      • Click Save Configuration, then Test Connection
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      • JTAG Connection window will pop-up. Confirm that the JTAG DR Integrity scan-test has succeeded:
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   5. Launch the Target Connection
      • Right click Target Connection ccxml file -> Launch Selected Configuration
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      • Right click on the R5_0 Core and click Connect Target
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      • If the output Console is not visible, click View -> Console in CCS. Observe the console output. Connecting to the target automatically loads GEL (General Extension Language) files to the R5F core selected to Initialize the AM26x device. This includes configuring device clocks, enabling peripheral clocks, and unlocking control registers.
        • GEL files can also be manually loaded to the device. Right click the R5_0 Core and click Open GEL Files View 
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        • A window displaying GEL files will open. Device-specific GEL files can be found at {CCS_install_path}/ccs[version]/ccs_base/emulation/gel/[device_name]
   6. If no errors are observed in the output console, JTAG connection to the device is verified.
5. One JTAG connection is verified, run the Hello World example binary from the MCU+ SDK on the AM26x device to verify proper program loading and output.
   1. Ensure the latest MCU+ SDKfor your AM26x device is downloaded
      • AM263x: https://www.ti.com/tool/MCU-PLUS-SDK-AM263X 
      • AM263Px: https://www.ti.com/tool/MCU-PLUS-SDK-AM263PX 
   2. In Code Composer Studio, click File -> Import
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   3. Select CCS Projects
   4. In the Import window, select Browse and navigate to mcu_plus_sdk_{AM26x_device_name}_{version}\examples\hello_world\am263px-cc\r5fss0-0_freertos\ti-arm-clang
   5. Click Finish
   6. Build the project
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   7. When the project has completed building, connect to the R5_0 core of the target connection (if not done already - see section 4.e of this FAQ)
   8. In the CCS toolbar, click Run -> Load -> Load Program
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   9. In the Load Program window, select Browse Project and navigate to the Release folder of the CCS project
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   10. Click OK to load the project binary file to the AM26x device R5_0 core
   11. Click the Play (Resume) button in the CCS toolbar to run the binary on the AM26x device
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   12. Observe the output in the console. The proper output is below:
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The basic checks for custom PCB bring-up with an AM26x device are now complete. For more in-depth debug questions, please post on the TI E2E forums for technical support from TI engineers.