RM57L843: Atomic variable access support in TI Code composer

Ravi Teja Darbha

Part Number: RM57L843

Tool/software:

Hi,

I have a requirement where I would like to access a variable updated by interrupt handle within a freertos task. In doing so, I do not want to disable and enable interrupt to access that variable. I am instead looking to atomically access that variable within the freertos task. Does TI Code Composer Studio compiler provide support for atomic access. If so is there a document that lists al those functions?

Ravi

7 months ago

0 Ravi Teja Darbha 7 months ago

Intellectual 305 points

Jut checking if I can get an update on this?

Thanks!

0 jagadish gundavarapu 7 months ago in reply to Ravi Teja Darbha

TI__Guru 63035 points

Hi Ravi,

I don't think we have atomic memory in the Hercules devices (that includes RM57x). Actually, it is not about TI code composer studio, basically the core should support the atomic access (single cycle access). Unfortunately, we don't have this support.

You already mentioned one way of disabling and enabling the interrupts, i think the other way could be to use either semaphore or mutex to control the access. I think in this way you no need to disable the interrupts.

--
Thanks & regards,
Jagadish.

0 Ravi Teja Darbha 7 months ago in reply to jagadish gundavarapu

Intellectual 305 points

Hi Jagadish,

By atomic, I don't think I meant single cycle access. It could take how many ever cycles it want. But my only requirement is the memory access is done atomically. Which means the arm core provides architectures support by providing instructions such as ldrex and strex tto atomically acces data and it is not interrupted by interrupts and using that the atomic access is constructed. Every toolchain provides it. Infact it is even mentioned in TI compiler user manual on page 82. But it only talks about ldrex and strex support provided in cortex R5 microcontrollers for implementing atomic access but nothing on api's provided by TI compiler library using these instructions for atomic access.

Here is what it is mentioned on the user manual

On ARM V7A8 (Cortex-A8), ARM V7M3 (Cortex-M3), ARM V7M4 (Cortex-M4), ARM V7R4 (Cortex-R4), and
ARM V7R5 (Cortex-R5)), atomic operations are implemented using processor-supported exclusive access
instructions.

Here is the TI compiler user manual for your reference.

www.ti.com/.../SPNU151W