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TM4C1294NCPDT: Adding large flash memory to Tiva

Doug Baker
Genius 3400 points
Part Number: TM4C1294NCPDT

Tool/software:

I need to add more external flash to a TM4C1294NCPDT CPU.  I assume the best way to do this is by using the USB or SPI interface but if there is something better let me know.  Most flash devices support SPI and I think some can use USB.  I don't need a file system because we just need to "stream" some large amount of data in and out of flash via Ethernet. 

If the flash memory size needed is 1 GigBit, what memory would be recommended and what is the best performance that could be expected?  

The project uses TM4C1294NCPDT, CCS 8.3.0, TIRTOS 2.16.1.14.

Thanks,

Doug

  • 0
    TI__Guru**** 183536 points

    Hi Doug,

      In addition to serial flash memory using SPI interface, TM4C129 also support EPI (External Peripheral Interface) where you can connect a parallel flash device using EPI's 16-bit Host-Bus Mode. Please refer to the datasheet for details on the maximum memory size supported. Note that there is no hardware command write support for Flash memory devices; this mode should only be used for Flash memory devices programmed at manufacturing time. If a Flash memory device must be written and does not support a direct programming model, the command mechanism must be performed in software. Parallel memory would have offered better performance compared to serial memory but serial memory will be easier to implement. 

    ■ Host-Bus mode
    – Traditional x8 and x16 MCU bus interface capabilities
    – Similar device compatibility options as PIC, ATmega, 8051, and others
    – Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
    non-multiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
    no byte selects)

    – Support for up to 512 Mb PSRAM in quad chip select mode, with dedicated configuration
    register read and write enable.
    – Support of both muxed and de-muxed address and data
    – Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
    with support for external FIFO (XFIFO) EMPTY and FULL signals
    – Speed controlled, with read and write data wait-state counters
    – Support for read/write burst mode to Host Bus
    – Multiple chip select modes including single, dual, and quad chip selects, with and without
    ALE
    – External iRDY signal provided for stall capability of reads and writes
    – Manual chip-enable (or use extra address pins)

    11.4.3.3 Host Bus 16-bit Muxed Interface
    Figure 11-11 on page 842 shows how to connect the EPI signals to a 16-bit SRAM and a 16-bit Flash
    memory with muxed address and memory using byte selects and dual chip selects with ALE. This
    schematic is just an example of how to connect the signals; timing and loading have not been
    analyzed. In addition, not all bypass capacitors are shown.

  • 0 in reply to Charles Tsai
    Genius 3400 points

    The project we want to add memory to has most of the pins on the Tiva used so were probably limited with a serial interface. I think using SPI would be the easiest to implement but maybe if used USB it may have better performance (faster) but I'm not sure how the implementation would be if using USB.  I think it's possible to use a file system with USB but I'm not sure if the latest large memories are supported by the OS so the implementation may be more complex using USB over SPI.  We do have a free SPI port but the other pins that would be needed for quad SPI are used.

  • 0 in reply to Doug Baker
    TI__Guru**** 183536 points

    USB full speed is 12Mbit/s in theory but you won't achieve the 100% throughput due to the inherent USB overhead. Having SPI running at 60MHz in quad-mode may be as fast as USB or even better but you need to work out the calculation.

    For USB there is a example at C:\ti\TivaWare_C_Series-2.1.4.178\examples\boards\dk-tm4c129x\usb_host_msc that uses a filesystem.