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AM2432: network failure for am2432 with phy dp83822

cheng guo
Prodigy 180 points
Part Number: AM2432
Other Parts Discussed in Thread: SYSCONFIG, DP83822H

Tool/software:

Hi TI

We are using am2432 with an external phy dp83822, when we power up our system, sometimes network failed. 

It seems that the content of the frame is changed and sometimes there is no frames at all. But local network connection is link up and unplug and reinsert the internet cable make no sense.

We develop our software based on demo "mcu_plus_sdk_am243x_09_02_01_05\examples\networking\lwip\enet_lwip_cpsw", how can we debug this issue, we don't know the issue is in cpsw or external phy. 

We need your help. Thanks.

  • 0
    Prodigy 180 points

    Hi

    Here I add more info about this issue.

    issue description:

    In our application, am2432 send out udp frames after network startup. But sometimes frmaes sent out are chaned or do not send out frames at all.

    SDK version:

    mcu_plus_sdk_am243x_09_02_01_05

    hw version:

    AM2432BSDGHIALXR

    test steps:

    power up the board and then check if correct frames are sent out. 

    issue rate:

    sometimes issue occur less than 100 tests. sometimes more than 700 tests.

    reproduce on other boards:

    yes, we have reproduced this issue on different boards.

    pre-analysis:

    We read some cpsw registers when issue reproduced.

    0x0803a044 is always 0

    0x0803a064 register value changes 0x112f6f2c -> 0x11856fb8 -> 0x11b75d58 -> 0x11dbf3ae

    0x0803a068 is always 0

    0x0803a06c register value changes 0x613f -> 0x61e4 -> 0x6243 -> 0x629a -> 0x62e3

    0x0803a070 is always 0xc

    0x0803a074 is always 0x9

    0x0803a078 is always 0

    0x0803a07c register value changes 0x9cd18 -> 0x9d7bf -> 0x9de5b -> 0x9e784 -> 0x9eee0

    It indicates that sending frames is ongoing? 

    Thanks. Looking forward for your reply.

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points

    Hi ,

    Thanks for your query.

    You can refer below example on SDK 10.0 and check MAC loopback is working for you ar not?

    AM243x MCU+ SDK: Enet CPSW Loopback Example (ti.com)

    Hopefully, you referred documentaion on external PHY mangement

    AM64x MCU+ SDK: Ethernet PHY Integration Guide

    AM64x MCU+ SDK: Enet Migration Guide

    Are you able to connect/control PHY?

    Can you share UART console logs?

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Thanks for your help.

    I tested MAC loopback demo on SDK 10.0, we are using mac port 2 to connect to external phy dp83822.

    =============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
Setting in NO-PHY mode for MAC port 2
PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown: Port 2: Link down

Disabling clocks for ENET: 5, inst:0!
Test complete: PASS
=============================
 Enet Loopback: Iteration 2 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
Setting in NO-PHY mode for MAC port 2
PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown: Port 2: Link down

Disabling clocks for ENET: 5, inst:0!
Test complete: PASS
=============================
 Enet Loopback: Iteration 3 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
Setting in NO-PHY mode for MAC port 2
PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown: Port 2: Link down

Disabling clocks for ENET: 5, inst:0!
Test complete: PASS
=============================
 Enet Loopback: Iteration 4 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
Setting in NO-PHY mode for MAC port 2
PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown: Port 2: Link down

Disabling clocks for ENET: 5, inst:0!
Test complete: PASS
=============================
 Enet Loopback: Iteration 5 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
Setting in NO-PHY mode for MAC port 2
PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Received 5000 packets
Delete EnetApp_rxTask() and exit..
Transmitted 5000 packets 
Delete EnetApp_txTask() and exit..

 Port 0 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000


 Port 1 Statistics
-----------------------------------------
  rxGoodFrames            = 5000
  rxBcastFrames           = 5000
  rxOctets                = 2590000
  txGoodFrames            = 5000
  txBcastFrames           = 5000
  txOctets                = 2590000
  octetsFrames512to1023   = 10000
  netOctets               = 5180000
  ietRxSmdError           = 1
  txPri[0]                = 5000
  txPriBcnt[0]            = 2590000

Cpsw_handleLinkDown: Port 2: Link down

Disabling clocks for ENET: 5, inst:0!
Test complete: PASS
Loopback application completed
All tests have passed!!

    We refered these two document when we add dp83822.

    We are able to read  write phy registers by uart when issue occured, but we didn't find anything wrong, what registers to read or write when issue occured to debug this issue?

    Here I attach our board startup log.

    DMSC Firmware Version 9.2.8--v09.02.08 (Kool Koala)
DMSC Firmware revision 0x9
DMSC ABI revision 3.1

INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
[BOOTLOADER_PROFILE] Boot Media       : NOR SPI FLASH 
KPI_DATA: [BOOTLOADER_PROFILE] Boot Media Clock : 100.000 MHz 
KPI_DATA: [BOOTLOADER_PROFILE] Boot Image Size  : 778 KB 
[BOOTLOADER_PROFILE] Cores present    : 
r5f1-0
r5f0-0
KPI_DATA: [BOOTLOADER PROFILE] SYSFW init                       :      11762us 
KPI_DATA: [BOOTLOADER PROFILE] System_init                      :      13316us 
KPI_DATA: [BOOTLOADER PROFILE] Drivers_open                     :        282us 
KPI_DATA: [BOOTLOADER PROFILE] Board_driversOpen                :         70us 
KPI_DATA: [BOOTLOADER PROFILE] Sciclient Get Version            :       9857us 
KPI_DATA: [BOOTLOADER PROFILE] CPU load                         :      76730us 
KPI_DATA: [BOOTLOADER_PROFILE] SBL Total Time Taken             :     112020us 

Image Swap[N] loading done, switching to application ... [0|0|0]
SwapA AvaFlag FFFFFFFF!
SwapA Counter -1!
SwapB AvaFlag FFFFFFFF!
SwapB Counter -1!
INFO: Bootloader_runCpu:155: CPU r5f1-0  is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...

Enable Dynamic Protection Bit.
SwapA AvaFlag FFFFFFFF   	 SwapB AvaFlag FFFFFFFF   	 BottomA AvaFlag BABA8D8D   	 BottomB AvaFlag BABA8D8D   
SwapA Counter -1         	 SwapB Counter -1         	 BottomA Counter 1          	 BottomB Counter 2          
SwapA Length FFFFFFFF   	 SwapB Length FFFFFFFF   	 BottomA Length 8394E      	 BottomB Length 8394E      
Curr Swap A Bottom Swap B !
DatM init finish!
R0 set Mot flag to 5A.
Mot flag set to A5 by R1.
INIT_B 1
DONE 1
IMU IAM-20680HT connect success
==========================
      ENET LWIP App       
==========================
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 2 
Mdio_open:294 
PHY 1 is alive
phyAddMask is 0xa.
Enabling clocks!
EnetApp_initTsn:TSN app start done!
BotCtrl_vidInit
No valid code wheel cali data, use default.
Load all code wheel calidata and E zero data to motor core.
E zero data:
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TopCtrl_vidInit
[0]: Starting lwIP, local interface IP is 198.18.32.10
Cpsw_handleExternalPhyLinkUp:1245 
==========================up1
[LWIPIF_LWIP] NETIF INIT SUCCESS
Cpsw_handleExternalPhyLinkUp:1245 
==========================up1
Host MAC address-0 : 98:03:8a:7e:e8:81

Host MAC address-0 : 40:2c:76:08:4a:22

[1]: Starting lwIP, local interface IP is 192.168.1.201
[LWIPIF_LWIP] NETIF INIT SUCCESS
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 198.18.32.10
[1]status_callback==UP, local interface IP is 192.168.1.201
 Connecting to: 255.255.255.255:6699
u16ImuDataDestPort 6688
 Connecting to: 255.255.255.255:6688
 Connecting to: 255.255.255.255:7788

robosense >func:Difop_vidMainFunction, line:107, Send data failed (error = Unknown error)!!!
[0] link_callback==UP
[1] link_callback==UP
     11.939s : CPU load =  10.46 %
1
3
3008 is 1, now config 459
apply 367 459 registers.
apply 459 failed, reg addr = 0x7e04, write value = 0x1, read back value = 0x0.
broadcast: start sending data
broadcast: send data done
apply 459 failed, reg addr = 0x7e04, write value = 0x1, read back value = 0x0.
     16.939s : CPU load =   6.69 %
apply 459 registers finished.
apply 0 top registers.
apply top registers finished.
apply 3 bot registers.
W_0x83C0000C_0xF4000000
W_0x83C11028_0x01
W_0x83C04210_0x4650
apply bot registers finished.
     21.940s : CPU load =  20.93 %
     26.940s : CPU load =  24.33 %
imu read error 0xfffffffe.
i2c handle state changed to idle.
imu read error 0xfffffffc.
     31.940s : CPU load =  24.22 %

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    We also tested the phy loopback demo.

    =============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
EnetPhy_bindDriver: PHY 1: OUI:080028 Model:24 Ver:00 <-> 'generic' : OK

PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA31

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp: Port 2: Link up: 100-Mbps Full-Duplex

Assertion @ Line: 563 in ../loopback_test.c: EnetLpbk_verifyRxFrame(pktInfo, rxPktCnt) == true : failed !!!

    rxPktCnt stoped at 589 every test loop.

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points

    Hi ,

    Thanks for the logs.

    from PHY loopback logs..Look like received frame is not simlar to sent frame. can you check and confirm this?

    >> Assertion @ Line: 563 in ../loopback_test.c: EnetLpbk_verifyRxFrame(pktInfo, rxPktCnt) == true : failed !!!

    I will also check logs deeply and get back to you.

    Next week, I am on leave. So expect response by end of 1st week of novemenber.

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Sorry for late reply.

    I added some print in the demo.

    static bool EnetLpbk_verifyRxFrame(EnetDma_Pkt *pktInfo, uint8_t rxCnt)
{
    uint8_t *rxPayload;
    EthFrame *rxframe;
    uint8_t verifyRxpkt = 0xA5+rxCnt;
    bool retval = false;
    uint32_t i,j;
    uint32_t segmentLen, headerLen;
    bool incorrectPayload = false;

    rxframe = (EthFrame *)pktInfo->sgList.list[0U].bufPtr;
    rxPayload = rxframe->payload;

    if (pktInfo->sgList.numScatterSegments == 1)
    {
        for (i = 0; i < ENETLPBK_TEST_PKT_LEN; i++)
        {
            if((rxPayload[i] != verifyRxpkt))
            {
                EnetAppUtils_print("rxPayload is 0x%x, verifyRxpkt is %x\r\n", rxPayload[i], verifyRxpkt);
                retval = false;
                break;
            }
            retval = true;
        }
    }

    rxPayload is 0x43, verifyRxpkt is 41
    Assertion @ Line: 565 in ../loopback_test.c: EnetLpbk_verifyRxFrame(pktInfo, rxPktCnt) == true : failed !!!

    The packet payload is 0x43, is it some kind of outof order error?

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    I added some print and got the log below.

    =============================
 Enet Loopback: Iteration 1 
=============================
CPSW_3G Test
Enabling clocks!
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 1 
Mdio_open: MDIO Manual_Mode enabled

Open MAC port 2
EnetPhy_bindDriver: PHY 1: OUI:080028 Model:24 Ver:00 <-> 'generic' : OK

PHY 1 is alive
EnetMod_ioctl: cpsw3G.macport1: Module is not open

Cpsw_registerIoctlHandler: Failed to register IOCTL handler: -1, 1000502, 700ABA61

EnetPer_ioctl: cpsw3g: Failed to do IOCTL cmd 0x01000110: -1

Enet_ioctl: cpsw3g: IOCTL 0x01000110 failed: -1

Failed to set dscp Priority map for Port 1 - -1 
initQs() txFreePktInfoQ initialized with 16 pkts
Cpsw_handleLinkUp: Port 2: Link up: 100-Mbps Full-Duplex

tx 0xa6
tx 0xa7
tx 0xa8
tx 0xa9
tx 0xaa
tx 0xab
tx 0xac
tx 0xad
tx 0xae
tx 0xaf
tx 0xb0
tx 0xb1
tx 0xb2
tx 0xb3
tx 0xb4
tx 0xb5
rx 0xa6
rx 0xa7
rx 0xab
rxPayload is 0xab, verifyRxpkt is a8
Assertion @ Line: 566 in ../loopback_test.c: EnetLpbk_verifyRxFrame(pktInfo, rxPktCnt) == true : failed !!!

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points

    Thanks  for logs,

    Will check and get back to you by next week.

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Thanks for your help.

    We did some test in our production software. We can read or write phy or cpsw registers through uart.

    The ethernet frame content is totally wrong and even can not be recognized by wireshark. and sometimes the mac address is wrong.

    We found that when failure reporduced and we reset phy, the error still exist. But after we set phy register 0x42 to value 0x11, the error disappeared.

     

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points

    Hi c

    As PHY loopback and MAC loopback is working, but with some frame content wrong.

    Assuming this a custom board with AM243x + DP83822.

    Did you get schematic reviewed from TI-HW team.

    For SW related issues:

    Did you discable another unused port (CPSW-Port-1) in sysconfig ?

    From where these IOCTL errors coming from ?

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Our schematic is not reviewed because we didn't provide the whole schematic to TI, but we design the hw according to the evaluation board.

    For sw related issues, yes, the port-1 is not connected to 83822 but connected to fpga by MAC2MAC. and we just test port-2 for the test case.

    In addtion to our previous test, whatever we set the 0x42 TX_CLK phase shift register in our software value from 0x11-0x19, we can always reproduce the error, but when error happened, we change the register to another value which is differernt from the value set in the initialization, the error disappears. I think the error is most probably caused by this register. But we don't konw how to solve the issue.

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points
    cheng guo said:
    For sw related issues, yes, the port-1 is not connected to 83822 but connected to fpga by MAC2MAC. and we just test port-2 for the test case.

    This is a news for me

    Means, your custom board CPSW-port-1 is connected to FPGA using MAC2MAC connection ?

    and

    CPSW-port-2 is connected to DP83822 ?

    DP83822 is configured in RGMI or RMII mode?

    CPSW-Port-1 mode ?

    CPSW-port-2 mode ?

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Yes. for our custom board, CPSW-port-1 is connected to FPGA using MAC2MAC connection, CPSW-port-2 is connected to DP83822. CPSW-Port-1 is configured RGMII 1000Mbps mode, CPSW-Port-2 is configured RGMII 100Mbps mode.

  • 0 in reply to cheng guo
    TI__Expert 6771 points
    cheng guo said:
    Yes. for our custom board, CPSW-port-1 is connected to FPGA using MAC2MAC connection, CPSW-port-2 is connected to DP83822. CPSW-Port-1 is configured RGMII 1000Mbps mode, CPSW-Port-2 is configured RGMII 100Mbps mode.

    Hello Cheng guo

         so which connection has error, CPSW-port-1 or CPSW-port-2?

    Regards

        Semon

  • 0 in reply to Semon Zhang
    Prodigy 180 points

    Hello Semon

    CPSW-port-2 is connected to dp83822 chip, we can not get correct frames on ethernet, based on previous test, we think there is error in RGMII connection between CPSW-port-2 and dp83822.

  • +1 in reply to cheng guo
    TI__Mastermind 24280 points
    cheng guo said:
    Our schematic is not reviewed because we didn't provide the whole schematic to TI, but we design the hw according to the evaluation board.

    This is okay to not provide full schematic. But at least MAC to PHY RGMII connection as your below observation seems to be valid.
    I am trying to contact expert from PHY team as well on this.

    cheng guo said:
    we think there is error in RGMII connection between CPSW-port-2 and dp83822

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    Here I attach connection part of schematic, please check.

  • 0 in reply to cheng guo
    TI__Genius 12751 points

    Dear Ashwani.

    local customer Robosense team also reports this issue to PHY team, here is the E2E ticket.

    (+) DP83822H: Link up but the sending and receiving information is wrong. - Interface - INTERNAL forum - Interface - INTERNAL - TI E2E support forums

    please help contact with PHY expert also.

    thanks a lot!

    yong

  • 0 in reply to Yong Zhang
    TI__Mastermind 24280 points
    Yong Zhang said:
    (+) DP83822H: Link up but the sending and receiving information is wrong. - Interface - INTERNAL forum - Interface - INTERNAL - TI E2E support forums

    This thread is already assigned to PHY team only.

    Regards

    Ashwani

  • 0 in reply to cheng guo
    Prodigy 215 points

    Hello, are you Chinese? I have been debugging AM263x connection dq83822 recently, I have completed 83869 debugging, 83822 has been having problems, maybe we can communicate by phone or wechat

  • 0 in reply to ych_chn
    TI__Expert 6771 points
    ych_chn said:
    Hello, are you Chinese? I have been debugging AM263x connection dq83822 recently, I have completed 83869 debugging, 83822 has been having problems, maybe we can communicate by phone or wechat

    Hello Yuan

          yes I am TI FAE in China, you can mail to me about this case:
           semon_zhang@ti.com

    Regards

       Semon

  • 0 in reply to cheng guo
    Prodigy 215 points

    Hello, are you Chinese? I have been debugging AM263x connection dq83822 recently, I have completed 83869 debugging, 83822 has been having problems, maybe we can communicate by phone or wechat,

  • +1 in reply to Ashwani Goel
    TI__Genius 12751 points

    Dear Ashwani.

    update from customer.

    customer found the port of PHY need be set to RGMII mode on PHY side.

    customer did the first test with this setting, the signal is normal on TXCLK.

    customer will do more test to double confirm that. will update the status later.

    put this ticket in "Waitting for customer" state.

    thanks a lot!

    yong

  • 0 in reply to Ashwani Goel
    Prodigy 180 points

    Hi Ashwani

    After enalbed RGMII mode bit in 0x17 register of 83822. This error can not be reproduced. Thanks for your help.

  • 0 in reply to ych_chn
    Prodigy 180 points

    Hello 

    Yes I am chinese, how can I contact you?

  • 0 in reply to cheng guo
    TI__Mastermind 24280 points
    cheng guo said:
    After enalbed RGMII mode bit in 0x17 register of 83822. This error can not be reproduced. Thanks for your help.

    Thanks for update.

    Regards
    Ashwani

  • 0 in reply to cheng guo
    Prodigy 215 points

    my wechat is：ych_chn

  • 0 in reply to cheng guo
    TI__Genius 12751 points

    Dear Cheng.

    would you please help feedback if it has been solved by RGMII bit set in PHY? we can close this if it is.

    thanks a lot!

    yong

  • 0 in reply to Yong Zhang
    Prodigy 215 points

    Yes, I have solved the problem~

  • 0 in reply to ych_chn
    TI__Mastermind 24280 points

    Thanks Cheng and yong.

    Regards

    Ashwani

  • 0 in reply to Yong Zhang
    Prodigy 180 points

    Hi Yong

    Yes, it has been solved. Thanks for your  help.