Tool/software:
Hi Team AM243,
My customer has the following question about boot modes and in particular QSPI..
The primary boot mode in use is SPI boot mode, but they have QSPI (all 4 data pins connected), and want to move to QSPI boot mode.
TI has suggested they add QSPI reset in SBL by toggling reset pin on SPI bootflash to put back the flash into a clean state, and also suggested to connect reset line from SOC to the flash part. Since the ROM and APP FW can configure the SPI flash in a different way, when SOC resets, it should reset the flash part as well, then ROM can boot from a clean state; vice versa.
However, compared to the implementation w/ TI’s EVM, the customer's flash device doesn’t have a dedicated reset pin.
Based the flash device's datasheet,
1) Reset pin is the same pin as HOLD#, and it is the shared pin as DO3 for QSPI. So this reset pin is only available for SPI mode, not QSPI mode.
2) Is this a stopper for us to move to QSPI boot mode due to the fact that no reset pin is available for QSPI boot mode?
3) If we have to stay with 1s-1s-1s mode, I believe the bootROM uses 1s-1s-1s mode as well, do we still need to connect SoC’s reset to flash part?
TI had replied with..
The need for Reset is described in the below section of the TRM
4.4 Boot Modes
4.4.1 OSPI, xSPI, QSPI, SPI Boot
When using SPI, you could choose a 8 pin device that supports reset since this could be used to recover the attached device from any failure that makes the SPI device non responsive to software commands.
When using QSPI, you could use 8 pin but his device has limitation that a cold reset – power reset has to be performed to recover the device in case the device becomes non responsive to software command.
Follow-on customer ask..
Still have questions regarding whether it can cause failures when running QSPI mode in app FW then issue a warm reset (note that there is no QSPI reset here), which will go back to bootROM code which uses 1s-1s-1s mode. This is a possible issue.
Thanks, Merril
