RM46L852: Connections and layout of tracks for the RMII interface.

Part Number: RM46L852
Other Parts Discussed in Thread: DP83640,

Tool/software:

Hi, I am developing a prototype that uses the RMII interface to implement the ETHERNET communication. This prototype consists of the RM46L852 (MAC) and the DP83640 (PHY). On the other hand, I am using the 100BASE-TX.

As you know, the design of this protocol involves complying with a list of rules that ensure correct behavior. So, here is a list of the ones I have been able to accomplish and the ones I have not been able to accomplish. I would like to ask some questions about this topic and get your opinion and possible solutions. The rules are as follows:

• RMII and MII signals:
  • For xMII signals, a track length < 6 in (152.4 mm) is recommended. Yes
    
  • The length match of all xMII signals must be ≤ 3 mm. Yes
    
  • Signal pairs (for example: TXD_0 and TXD_1) must be rout in parallel. Making them as similar as possible to avoid problems with data synchronization. Yes
    
  • xMII signals should not be routed on adjacent copper layers, i.e. if you have a 4-layer PCB (F_Cu, In1_Cu, In2_Cu, and B_Cu) traces should not be routed on the F_CU and In1_Cu layer, nor on In2_Cu and B_Cu, but should be routed on the F_Cu and B_Cu layer. Yes
  • Sensitive signals such as the “REFCLK” clock signal should not be route in parallel with other signals. Yes
    
  • xMII signals must be separated from other xMII or other signals with a minimum “S or D” separation of at least 2 H. “H” being the thickness of the dielectric (Separation between layers). Yes
    
  • TXD signals must be separated from RXD signals to minimize electromagnetic interference. Yes
    
  • xMII signals must be located away from power signals or planes to prevent noise from coupling into the power signal. Yes
    
  • If power devices such as DC/DC converters are present and thus a power supply network that provides the required currents and voltages, it is advisable to route the xRMII signal traces on the outer copper layers and to provide a continuous ground plane on the adjacent copper layer. In such a way, there is always a continuous ground plane under the xMII signal traces. Yes
    
  • Traces must not cross a division between planes.

    

  • It is recommended that the PCI be at least four layers. Yes
    
  • xRMII signals should be considered Single-Ended type and must have an impedance value between 50-60 Ω. Yes
    
  • 50 Ω termination resistors. However, this feature is already implemented in the DP83640. Yes
    
  • It is recommended to minimize layer changes since they cause stubs and impedance discontinuities. Therefore, it is recommended to avoid or minimize the use of vias in the signal layout. In the event that there is no other option, it is recommended to use blind or buried vias. No
  • If there is a serious problem with crosstalk it is advisable to use paths connected to VSS or GND with some separation from the signal paths. This allows coupling to be reduced by a factor of x4. This provides a path for the return current to be directed to the ground plane and in turn helps to minimize the return current path. Yes. There is no such problem, but it has still been taken into account in the design.
  • If there is a serious problem with crosstalk, it is recommended to fill the space between high-speed signals, such as xRMII signals, with a ground plane. There is no such problem, but it has still been taken into account in the design.
• MDI signals:
  • It is recommended to use symmetrical copper planes on both sides of the differential signal. These should incorporate paths with the same separation distance, i.e., separation symmetry must be maintained to avoid common mode noise, which would affect the amplitude of the differential signal. Yes

    

  • If there is a continuous ground plane beneath the differential MDI signal, the insulation length between the top copper layer, where the differential signal is located, and the inner layer, where the ground plane is located, must be ≥ 2 W of the differential signal. Too short a length may introduce common mode noise. No
    
  • The length match of each differential signal pair must be ≤ 1 mm. Yes
    
  • MDI signals must be considered Differential type and must have a differential impedance value of 100 Ω. Yes
  • Each differential signal pair must be routed on the same copper layer, minimizing plane changes using vias. No
    
  • Each MDI pair must be routed in parallel to ensure differential coupling. Yes
    
  • Stubs should be avoided. Yes
    
  • The length of MDI signals must be < 3 in (76.2 mm). Yes
    
  • A separation of 5 · W must be achieved between each differential pair. No
• Clock: It is recommended to use a CMOS oscillator that has a maximum tolerance and stability of 0.005% (±50 ppm), a long-term stability (aging) of ±3 to ±5 per year, a maximum rise and fall time of 6 ns, a maximum jitter of 800 ps, ​​a maximum low logic level value of 10% VDD, a minimum high logic level value of 90% VDD, an output capacitive load of 15 pF and a minimum symmetry of 40% and a maximum of 60%. Yes
• Circuit:
  • A 49.9 Ω resistor with a 1% tolerance must be placed near each TD± and RD± pin, making a total of 4 resistors. A 0.1 μF decoupling capacitor must also be placed connected to a VCC plane by means of a via, one for TD± and one for RD±, making a total of 2 capacitors. In addition, the MDI signal tracks (TD± and RD±) must have a differential controlled impedance of 50 Ω to ground or 100 Ω. Finally, a 0.1 μF decoupling capacitor must be connected between TXCT and VDD and another between RXCT and VDD.
    
  • A 10 μF decoupling capacitor must be placed between the VDD and GND planes.
  • A 0.1 μF SMD decoupling capacitor should also be placed for the VDD pins. These capacitors should be placed as close to the VDD pins as possible to reduce EMI interference.

My schematic:

My PCI properties

Therefore, with these PCI properties I will get the following impedance values:

• Microstrip Impedance - Single-Ended: FR4 substrate, Dielectric thickness “H” (Layer spacing) of 0.12 mm, Frequency of 100 MHz, Track width “W” of 0.15 mm, Copper thickness “T” of 60 µm, Track spacing “S” of 0.15 mm and Length (max) of 45 mm for single-ended RMII signals and 56 mm for single-ended MDIO signals (Obtained from tracing tests). Therefore, a line impedance of 50 Ω will be obtained for Single-Ended signals.
• Microstrip Impedance - Differentials: FR4 substrate, Dielectric thickness “H” (Separation between layers) of 0.12 mm, Frequency of 100 MHz, Track width “W” of 0.125 mm, Copper thickness “T” of 60 µm, Separation between tracks “S” of 0.2 mm and Length (max) of 75.5 mm for the differential MDI signals. Therefore, a differential impedance of 98 Ω will be obtained.

So, I have a number of questions about the rules I'm not following:

• It is recommended to minimize layer changes since they cause stubs and impedance discontinuities. Therefore, it is recommended to avoid or minimize the use of vias in the signal layout. In the event that there is no other option, it is recommended to use blind or buried vias. No . I cannot comply with this rule since I have xRMII signals in both the top layer (F_Cu) and the bottom layer (B_Cu). Therefore I used through hole. Would this situation affect the signals too much? I attach you a picture where it appears this situation for the TXD_0 signal.
  
• 50 Ω termination resistors. However, this feature is already implemented in the DP83640. Yes. This rule is accomplished without the need to add external termination resistors using the DP83640 to the RXD0, RXD1, CRS_CRS_DV, RX_ER and RX_DV. This signals are transmitted from DP83640 (PHY) to RM46L852 (MAC). However, Should this method also be applied to TX signals (those signals transmitted by the RM46L8652 (MAC) to the DP83640 (PHY)) by placing an external terminating resistor near the TXD signal of the RM46L852 (transmitter)? If so, should its value be 50 ohm? Would it affect only the TX0 and TXD1 signals or also the TX_EN signal?
• If there is a continuous ground plane beneath the differential MDI signal, the insulation length between the top copper layer, where the differential signal is located, and the inner layer, where the ground plane is located, must be ≥ 2 W of the differential signal. Too short a length may introduce common mode noise. No. I cannot comply with this rule because my Dielectric thickness “H” (Separation between layers) is 0.12 mm. Would it make sense to eliminate the copper dedicated to the ground plane throughout the section where the corresponding MDI trace is located?
  
• A separation of 5 · W must be achieved between each differential pair. No. I had defined a different distribution of the TD and RX MDI type tracks. I attach the image, the black marking is to indicate that there is a ground plane around and between the TD and RD signals. Do you recommend that I follow the distribution specified in the rule?