AM2434: Use pru(icss) rgmii interface to communicate with fpga

Hi, I have assigned this thread to an expert who can talk about an option

Hi Thomas,

so i tested the Sorte_G am243x example on two am243x-evm boards since i dont have the lp at hand. Since the eth phy are the same on both boards the example should work, except for the LEDs and the Controller, Device selection which i did manually. 
How does the pru cores communicate with the R5F Cores?

Maybe i missed something but from my understanding the R5F cores only load the pru firmware and start the pru cores but dont exchange any data with them?

Thanks again.

- Lucas

Hi Lucas,

Let me address your question.

The PRU device code triggers an ARM event after it receives and stores the controller OUT data frame.

In File ioex_g.asm:

        ; generate interrupt to notify APPL

        ldi            R31, IRQ_OUT_DATA_READY               ; generate int

In the ARM there is an ISR in file sorte_g_app.c that receives this interrupt.

static void PRU_IsrFxn()

Regards,

 Thomas

Hi Thomas,

thanks again for the fast reply. I found this ISR but it never seems to enter it. Maybe a configuration issue with the evm board.
For the communication part, to get the data i have to read the from PRU_ICSSG1_DRAM0_SLV_RAM with offset 20 as stated in the API?
How can i send data from the R5F to the pru to send this data out?

Kind regards,

Lucas

Hi Lucas,

When you ported the SW from LP to EVM, did you port also the interrupt configuration in SYSBIOS? Maybe this is missing, and PRU to ARM interrupt is not configured...

The SORTE_G device uses a memory shared interface to send the IN data or receive the OUT data. I don't recall from the top of my head now the addresses in PRU shared memory, but recall that the memory location is configurable by the ARM application code.

1. From looking at the IO_EX code, the IN data (data send from device to controller) is the following:

IOEX_CMP0_LOAD_DATA:
; load payload from PRU data memory
    ldi		TEMP_REG_1.w0, DEVICE_INDATA_FRAME_BUFFER_PTR
    lbco	&TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, TEMP_REG_1.w0, 2
    lbco	&R2.b0, PRU1_DMEM_CONST, TEMP_REG_1.w0, b0

DEVICE_INDATA_FRAME_BUFFER_PTR has the memory base pointer as set by the ARM application. The data bytes that are transmitted do reside in PRU1 data ram (PRU1_DMEM_CONST).

2. The OUT data (data that is received by the device from the controller) 

	; calculate write pointer
	lbco	&TEMP_REG_1.w0, ICSS_SHARED_RAM_CONST, DEVICE_MASTER_FRAME_BUFFER_PTR, 2
	add		TEMP_REG_1.w0, TEMP_REG_1.w0, RX_BYTE_CNT
	SBCO	&R2, PRU1_DMEM_CONST, TEMP_REG_1.w0, 32

Here DEVICE_MASTER_FRAME_BUFFER_PTR has the base address as set by the ARM application. The data bytes that are getting 
transmitted do reside also in PRU1 data memory (PRU1_DMEM_CONST)

The ARM application needs to interface with the memory in PRU1_DMEM to either send data, or receive data.
Let me know if you have additional questions.
Regards,
 Thomas

Hi Thomas,
i got the example mostly working  now, i can transmit data by changing it in the debug memory viewer and restarting the prus.

Is it possible to have the PRU running continuously and automatically start transmission on data change or interrupt triggering?

Where exactly can i configure the PRU to ARM Interrupt in sysconfig? 

Thanks and regards
Lucas

Hi Lucas,

Sorry for the delay because of holiday season.

The SORTE protocol periodically sends the data over Ethernet in a loop, regardless if anything changed in the data array.

PRU interrupts are configured in the PRU (ICSS) section - see screenshot.

Regards,

 Thomas

Hi Thomas,

thanks for the reply.

I got a step further and try to output data directly using the pruicss MII_G_RT Module to the highspeed connection header. Can the module create its data clock or is an external clock source needed? I couldn't find any output signal using the io link breakout board.
I tried configuring the pinmux from the syscfg->pru(icss)->additional icss settings->mii_g_rt tab and adapted the pru assembler register config.

Regards

Lucas