AM2432: PLL Fix in SDK9.2

Sigma Delta is from SDK 09.01.00.06 - Single Core no load share (ICSSG1 PRU1)

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1327675/mcu-plus-sdk-am243x-sigma-delta-jitter-noise-when-adjusting-iep-reset-timer

Please look at the last comment of Ram - that solved the issue described in this ticket

Also:

We are doing the following:

    /* Configure the SYNCI/SYNCO mapping to tie the three PWM groups together and have PWM0 SYNC from Time Sync Router 38 */
 CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE+CSL_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL(2<<CSL_MAIN_CTRL_MMR_CFG0_EPWM0_CTRL_SYNCIN_SEL_SHIFT));
 

   /* Time Sync Router input 25 (ICSSG1 IEP0 SYNC0) -> Time Sync Router output 38 (0x26 + 4 = 0x2A + Time Sync Router Base */
    CSL_REG32_WR(CSL_TIMESYNC_EVENT_INTROUTER0_CFG_BASE + ((38 * 4) + 4), (0x10000 | 25));

Please look at the following pictures:

Here you can see a software measurement that shows how much time passes between each Sync0 task.

ECAT cycle time is 2mSec.

You can see a jitters all around the signal and a very big jitter occasionally of around 15uSec.

Also note that first jitter is a shorter call and then it seems like it compensates with a delay.

Here you can see a record of the time delta between the Sync0 SW isr signal to the Sigma Delta ISR call.

You can clearly see that with time there is a drift

Hi Ariel,

I think you provided the details in the wrong thread. You may need input to the below thread for discussing SYNC0.

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1502768/am2432-failure-to-synchronize-sync0-with-pwm

This thread is mainly to discuss the PLL fixes, thanks.

Kevin

Hi Kevin

Kevin Peng said:

Actually customer already used SDK9.1 for mass production. Customer wants to know the impact for the above two PLL issue if they still use SDK9.1 Is this issue the same as the errata below?

There is no easy way to objectively quantify the impact of the PLL errata. See the below from the i2424 explanation.

Additionally, even on susceptible devices, the loss of lock is intermittent, but when it
occurs, dependent circuitry runs at an incorrect frequency; this wrong frequency can show
up as slow algorithm execution or communication failures.

Recommendation is to get the fix for this errata by updating the SYSFW version to SDK10.0 or later. These are supposed to be backward compatible and can be update by referring to the below developer note from the RTOS SDK.

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/11_00_00_15/exports/docs/api_guide_am64x/SYSFW_PLL_UPDATE_GUIDE.html

Regards

Karan

Hi Karan,

Customer is using AM24, and the latest SDK version is SDK9.2, could they follow the same guide? And is SDK9.2 in AM24 the same as SDK10 in AM64 for this PLL part?

Thanks,

Kevin