Tool/software:
Hi experts,
I’d like to revisit a topic that was discussed earlier but, in my view, still lacks a conclusive answer:
AM2431: XIP memory map write (MRAM)
The question is whether the OSPI peripheral (which essentially operates as Quad-SPI on the ALX) can be used to achieve fully memory-mapped access to an external SPI PSRAM.
Specifically, I’m aiming to read from and write to variables on the external RAM directly via pointers, as if it were standard memory.
Memory-mapped reads are clearly supported due to the typical flash-XIP use case. However, according to section 12.3.2.4.9 OSPI Direct Access Controller (DAC), memory-mapped writes should also be possible:
Direct access refers to the operation where data interface accesses directly trigger a read or write to FLASH memory. It is memory mapped and can be used to both access and directly execute code from external FLASH memory.
The sector-erase required for flash is manually done via STIG, which could therefore be easily omitted if PSRAM is connected.
As example, i am considering a PSRAM chip like the "QUAD RAM" shown here: https://www.issi.com/ww/pdf/SerialRAM.pdf
It supports a flash-compatible SPI interface, which i interpre to mean that the generated opcodes from the OSPI peripheral should be compatible:
JEDEC standard Quad I/O with DS NOR Flash Compatible Interface (4S-4D-4D)
In theory, this setup could work, but I’m very interested in hearing from TI experts or anyone who has attempted this.
Has anyone successfully implemented memory-mapped read/write access to external SPI PSRAM using OSPI?
Additionally, I’m unsure whether the CPU and cache controller fully support this mode in the way I’d like—specifically for seamless pointer-based access to external RAM.
This capability would be a significant advantage for the Sitara controller. The 2MB of internal SRAM is insufficient for our application, and we cannot use the larger ALV package that supports DRAM and GPMC.
While XIP from flash could help relocate code, our primary need is to extend RAM for large data buffers, making external PSRAM a potentially ideal solution.
Thanks in advance for your insights and experiences!
Best regards,
Stefan
