TMS570LC4357: EMS 2.3 Bus Error on Devboard, but not on custom board

Paul Sheppard

Part Number: TMS570LC4357
Other Parts Discussed in Thread: UNIFLASH, HALCOGEN,

Hello,

Having an issue with the Launchpad devboard (and on-board debugger), which I'm not seeing on our custom board using a segger J-Link.

As some point during start-up, but after main(), I'm finding the old EMS 2.3 ECC error occuring.

I've been through every article I can find, but I'm at a loss as to what's causing it.

A selection of the posts I've referenced:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/681586/compiler-tms570lc4357-nowecc-versus-linker-to-generate-ecc

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/633100/tms570lc4357-cortex-r5-core-fatal-bus-error-on-esm-for-tms570lc43x-causing-nerror-pin-to-become-active

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/776854/tms570lc4357-unexpected-ecc-errors-esm-2-3-when-flashing-start-of-flash-using-f021-api

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1323981/tms570lc4357-esm-group-2-channel-3-error-because-of-speculative-instruction-fetch-operation-issue

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1010835/tms570lc4357-source-of-cortex-r5f-core-errors-properly-initializing-flash-ecc

And more besides.

I've set the debugger to gernerate the ECC, I've set the linker to generate the ECC, both produce eactly the same results. Also gets stuck in_SL_Kickoff_STC_execution on first running. After restarting I get the ESM.

Cache is disabled.

Seems to have something to do with initialising the FEE module. Removing that seems to make it tentatively work. Of course I can't just work without it though.

Thanks.

7 months ago

0 jagadish gundavarapu 7 months ago

TI__Guru* 77906 points

Hi Paul,

I never came across this issue before!

We have one internal AI tool which can analyze all the old issues along with all the documentations of this device, when i provided your question to this tool i got some suggestions valid suggestions from it. Could you please check them once.

Root Cause - Likely Debugger Flash Programming Difference

The fact that you're seeing this error on the LaunchPad with the on-board XDS110 debugger but NOT on your custom board with the J-Link strongly suggests a flash programming/ECC generation difference between the two debuggers.

Key Issues to Address:

1. ECC Generation Method Conflict You mentioned trying both debugger-generated ECC and linker-generated ECC with the same results. However, there's a critical point: you cannot use both methods simultaneously. When using linker ECC generation (with the ECC directive in your linker command file and --ecc=on option), you MUST disable the AutoEccGeneration option in your flash programming tool/debugger settings.

2. FEE Module Initialization Issue The fact that removing FEE module initialization makes it "tentatively work" is a strong clue. The FEE (Flash EEPROM Emulation) module requires proper ECC initialization for the flash sectors it uses. If the ECC isn't properly generated for the FEE region during programming, you'll get ESM 2.3 errors when the code tries to access those areas.

3. STC (Self-Test Controller) Issue Getting stuck in _SL_Kickoff_STC_execution on first run suggests the self-test is detecting an issue, likely related to improperly initialized flash/ECC.

Additional Checks:

Verify Flash Wait States are properly configured for your clock frequency
Check if cache is truly disabled - verify SCTLR register settings
Ensure proper flash bank initialization before FEE module access
Check your FEE module configuration - verify the flash address ranges don't conflict with your code/data sections

Debugging Steps:

Read the ESM Status Registers to confirm it's exactly ESM Group 2, Channel 3 (Flash ECC error)
Check the Flash ECC Status Registers (FEDACSTATUS, FUNCERRADD, etc.) to see which address caused the error
Compare the .out file generated when programming with XDS110 vs J-Link - check if ECC sections are present

--
Thanks & regards,
Jagadish.

0 Paul Sheppard 7 months ago in reply to jagadish gundavarapu

Prodigy 130 points

Hi Jagadish,

Yeah, that's pretty much summarises what those threads say.

I have fixed the Flash7 EEC region though:

    ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0)  >> 3))
                   length=(size(FLASH0)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH0 }


/* Bank 1 ECC */
    ECC_FLA1 (R) : origin=(0xf0400000 + (start(FLASH1)  >> 3))
                   length=(size(FLASH1)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH1 }

/* Bank 7 ECC */
    ECC_FLA7 (R) : origin=(0xf0100000
                   length=(size(FLASH7)  >> 3)
                   ECC={algorithm=algoL2R5F021, input_range=FLASH7 }

I had a + (start(FLASH7) >> 3)) which shouldn't have been there.

I'm digging in further and I do seem to get some odd exceptions here and there, one consistent one is the PCR register.

Confirmed by both the exception LR and the DFAR, it seems that:

pcrREG2->PSPWRDWNCLR2 = 0xFFFFFFFFU;

in periphInit() causes a data abort.

Very odd.

EDIT: In fact I can't even read PCR 2 in the debugger register list window. PCR1 & 3 are readable. 2 is not!

0 jagadish gundavarapu 7 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

I had a launchpad board,

Is it possible to share your complete project for debugging at my end?

--
Thanks & regards,
Jagadish.

0 Paul Sheppard 7 months ago in reply to jagadish gundavarapu

Prodigy 130 points

Hi Jagadish,

I've paired the code down to a minimum(ish), it does seem to be FEE related.

In cutting code out I found that it's the call to TI_Fee_MainFunction()

Is there a more private way of sharing the project?

0 jagadish gundavarapu 7 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

I sent you friend request, please accept it, once you do accept then we can do private chat on forum.

Thanks & regards,
Jagadish.

0 Paul Sheppard 7 months ago in reply to jagadish gundavarapu

Prodigy 130 points

Accepted and message sent, thanks!

0 Paul Sheppard 6 months ago

Prodigy 130 points

I seem to be moving sideways.

So I've removed:

--fill_value=0xFFFFFFFF

From the.cmd file - I thought this was needed for the ECC stuff, but I see now it just sets the uninitialed default value and it interfered with the FEE module, which expected the memory to be zeroed.

I discovered there's another start up file in HalCoGen examples and I've ported that. In there is a bunch of defines to enable tests:

#define STC_ENABLE                0
#define PBIST_ROM_ENABLE          0
#define PBIST_L2RAM_ENABLE        0
#define PBIST_PERIPHRAM_ENABLE    0
#define PBIST_VIM_ENABLE          0
#define L2RAMECCCHECK_ENABLE      0
#define FLASHECCCHECK_ENABLE      0
#define PERIPHRAMECCCHECK_ENABLE  0
#define EFUSETEST_ENABLE          0
#define CCMR5TEST_ENABLE          0

I've found if any of them are enabled, interrupts don't work at all. It gets to main(), and the I&F bits are 0 in CPSR. but my RTI timer doesn't fire.

0 jagadish gundavarapu 6 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

Could you please refer my last comment in below thread once:

(+) TMS570LC4357：FLASH ECC Problem - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

This is very useful in this context, it seems like same issue you are facing.

--
Thanks & regards,
Jagadish.

0 Paul Sheppard 6 months ago in reply to jagadish gundavarapu

Prodigy 130 points

Yes, I've got all that in place, along with palign(32) and fill=0xffffffff on each of the flash sections.

Unfortunately it doesn't seem to work, need to have auto ecc on in the debugger. I use groups in the cmd file to generate CRCs. Maybe that interferes?

As things stand at the moment, I have to disable the 2 PERIPHRAM's and STC, and auto ECC calc needs to be on, for things to work.

0 Paul Sheppard 6 months ago in reply to Paul Sheppard

Prodigy 130 points

Another step forward:

Got the linker ecc generation working by removing the ti_fee* code from RAM:

    flashAPI: palign(32), fill=0xffffffff
    {
    	*Fapi_UserDefinedFunctions.obj (.text)
     	// *bl_flash.obj (.text)
     	// *ti_fee_* (.text)
     	--library= "*/F021_API_CortexR4_BE_L2FMC_V3D16.lib" (.text)
	} LOAD = BOOT, RUN = RAM, table(flashCpyTbl)

Leaving just the lib

I've noticed that the example had bl_flash running from RAM, but does it need to?

STC still won't work though. Data Entry exception clearing CAN errors

0 jagadish gundavarapu 6 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

Paul Sheppard said:
I've noticed that the example had bl_flash running from RAM, but does it need to?

Yes, it does need.

The reason is explained in below threads:
(+) TMS570LC4357: Problems with executing code and erasing on the same bank - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LS0432: IS IT POSSIBLE TO FLASH WRITE DATA IN BANK0 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Paul Sheppard said:
STC still won't work though. Data Entry exception clearing CAN errors

STC is sensitive to ECC.

Before STC, all flash sections should be initialized with proper ECC.

--
Thanks & regards,
Jagadish.

0 Paul Sheppard 6 months ago in reply to jagadish gundavarapu

Prodigy 130 points

I think I've got the flash EEC nailed now.

So from earlier:

Paul Sheppard said:
I'm digging in further and I do seem to get some odd exceptions here and there, one consistent one is the PCR register.

Confirmed by both the exception LR and the DFAR, it seems that:

pcrREG2->PSPWRDWNCLR2 = 0xFFFFFFFFU;

in periphInit() causes a data abort.

This describes the symptoms I've been seeing:

TMS570LC4357: Data abort exception after software reset

But the fix didn't work for me. I still see this occur in either CAN, PCR or reading the ADC calibration from OTP, or it works!

Though that might mean I could remove the cache and mpu disable calls I've put in at the very start of _c_int00()

Honestly, with the variety of symptoms going on, I think multiple issues are occurring. Sometimes the debug build will work, but the release won't. sometime it'' require a few debugger restarts to get to main()

Ensuring that cache and mpu is disabled from reset helped (must remain in place on SW restart?)

One of the issues I'm seeing now is interrupts are not firing. Mode is system (0b11111), IRQ & FIQ bits of cleared. The RTI is running, but no interrupt. This occur if I enable any of STC_ENABLE, PBIST_PERIPHRAM_ENABLE or PERIPHRAMECCCHECK_ENABLE. The rest can be on and it'll work (mostly).

Just to clarify (and you can see from the code I sent) Once init is complete a main while loop is started with the idle command. The RTI should trigger every ms and wake the processor. The processor never wakes up in this condition.

Oh, and have put breakpoint on the IRQ and FIQ vectors. FIQ gets hit 3-4 times to service the tests, IRQ not hit at all.

0 Paul Sheppard 6 months ago in reply to Paul Sheppard

Prodigy 130 points

To further confound things, in disabling STC_ENABLE, PBIST_PERIPHRAM_ENABLE or PERIPHRAMECCCHECK_ENABLE, it'll only the debug build will run, not the release.

I guess that means the the MPU, memory layout, cache, and whatever else settings are correct. Suggests a timing issue or something?

An example of an attempt to run release. (This is still using the HalCoGen example SL start-up file)

Debug ->

Stuck in PBIST_VIM_ENABLE PBIST fail

Restart ->

Prefetch abort, LR: 0x08080004, DFAR: 0xFCFF1204 (Pcr2_MstIdEna), IFAR: 0x08080000

Restart ->

Gets to main()

Start ->

Stuck waiting for FEE to become idle

Restart ->

Stuck in idle (no interrupts)

0 jagadish gundavarapu 6 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

Interrupts Not Firing When Self-Tests Are Enabled

Your observation that STC_ENABLE, PBIST_PERIPHRAM_ENABLE, or PERIPHRAMECCCHECK_ENABLE prevent interrupts from working is critical. This suggests:

Root Cause: The self-test controller (STC) and PBIST tests can affect the VIM (Vectored Interrupt Module) state. According to the documentation, the STC provides diagnostic coverage on both the CPU core and the VIM itself. When these tests run, they may leave the VIM in an unexpected state.

Recommendations:

Re-initialize VIM after self-tests complete: After running STC/PBIST tests, you must re-initialize the VIM interrupt vector table and ensure it's properly configured
Check VIM ECC: The VIM has its own ECC checking that must be properly initialized. Ensure the interrupt vector table has valid data and corresponding ECC check bits
Clear error flags: After self-tests, clear the UERR and SBERR flag registers and error address registers

// After self-tests complete:
// 1. Re-initialize VIM interrupt vector table
// 2. Enable VIM ECC (write 0xA to enable)
// 3. Clear any pending interrupt flags
// 4. Re-enable FIQ/IRQ in CPSR

Debug vs Release Build Differences

The fact that debug builds work, but release builds fail strongly suggests timing-dependent initialization issues related to compiler optimization

Root Causes:

Optimization removes delays: Release builds with higher optimization may remove implicit delays that mask initialization timing issues
Variable caching: Optimized code may cache peripheral register values instead of re-reading them

--
Thanks & regards,
Jagadish.

0 Paul Sheppard 5 months ago in reply to jagadish gundavarapu

Prodigy 130 points

So this:

e2e.ti.com/.../6184201

Solved most of the issues I hade here.

Some values (such as a couple of cpy_tbl addresses) were being stored in registers used in _memInit_() ) which were then of course corrupted by the call.

I'm very surprised no one has noticed this before! That it's not caused other problems

There were other changes needed to the HalCoGen example_SafetyLib.c

SL_ESM_Init(&esmCallBackFunction); is called very early in processing, but since PBIST_L2RAM_ENABLE clears memory, it shouldn't be called before it. I moved it down all the way to before _coreEnableIrqVicOffset_();

0 jagadish gundavarapu 5 months ago in reply to Paul Sheppard

TI__Guru* 77906 points

Hi Paul,

Paul Sheppard said:
Solved most of the issues I hade here.

Good to hear that Paul!

Paul Sheppard said:
Some values (such as a couple of cpy_tbl addresses) were being stored in registers used in _memInit_() ) which were then of course corrupted by the call.

I'm very surprised no one has noticed this before! That it's not caused other problems

There were other changes needed to the HalCoGen example_SafetyLib.c

SL_ESM_Init(&esmCallBackFunction); is called very early in processing, but since PBIST_L2RAM_ENABLE clears memory, it shouldn't be called before it. I moved it down all the way to before _coreEnableIrqVicOffset_();

Your anology seems to be correct. However i need to test it in practical. Anyway now you are unblocked, good to hear that. I will spend some time on this later and verify it from end.

--
Thanks & regards,

Jagadish.

0 Paul Sheppard 5 months ago

Prodigy 130 points

OK, so here's my working HL_sys_startup.c based on the HalCoGen example TMS570LC4357 example_SafetyLib.c, free of charge (despite taking ~240 of my man hours to fix).

clearcache.h contains the header for _memInitNeo_(), which is just an adapted version of _memInit_() exchanging R4-R12 for R0-R3 as per RE: TMS570LC4357: _memInit_() clobbers registers - Needs to be forced inlined

The copy tables are for my flash driver and exception jump table copies to RAM

/** @file HL_sys_startup.c 
*   @brief Startup Source File
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains:
*   - Include Files
*   - Type Definitions
*   - External Functions
*   - VIM RAM Setup
*   - Startup Routine
*   .
*   which are relevant for the Startup.
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */


/* Include Files */

#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_sys_vim.h"
#include "HL_sys_core.h"
#include "HL_esm.h"
#include "HL_sys_mpu.h"
#include "HL_errata_SSWF021_45.h"

/* USER CODE BEGIN (1) */
#include "sl_api.h"
#include "sl_types.h"
#include "HL_errata.h"
#include "HL_reg_dma.h"
#include "HL_reg_can.h"
#include "HL_reg_het.h"
#include "HL_reg_htu.h"
#include "HL_reg_mibspi.h"
#include "HL_reg_adc.h"
#include "HL_reg_efc.h"
#include "HL_reg_stc.h"
#include "HL_reg_pbist.h"
#include "HL_sys_core.h"
#include <cpy_tbl.h>
#include "HL_sys_cache.h"
#include "sl_priv.h"
#include "HL_can.h"
#include "clearcache.h"
/* USER CODE END */

/* USER CODE BEGIN (2) */
extern uint32                ulHighHandlerLoadStart;
extern uint32                ulHighHandlerLoadEnd;
extern uint32                ulHighHandlerSize;
extern uint32                ulHighHandlerStartAddr;
extern uint32                ulHighHandlerEndAddr;
extern void ESM_ApplicationCallback (uint32 grp_channel, uint32 param1, uint32 param2, uint32 param3);
extern COPY_TABLE ramIntvecsCpyTbl;
extern COPY_TABLE flashCpyTbl;
/* USER CODE END */

/* External Functions */

/*SAFETYMCUSW 218 S MR:20.2 <APPROVED> "Functions from library" */
extern void __TI_auto_init(void);
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(main should be declared by the user)" */
extern int main(void);
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 354 S MR:NA <APPROVED> " Startup code(Extern declaration present in the library)" */
extern void exit(int _status);


/* USER CODE BEGIN (3) */
#define STC_ENABLE                1
#define PBIST_ROM_ENABLE          1
#define PBIST_L2RAM_ENABLE        1
#define PBIST_PERIPHRAM_ENABLE    1
#define PBIST_VIM_ENABLE          1
#define L2RAMECCCHECK_ENABLE      1
#define FLASHECCCHECK_ENABLE      1
#define PERIPHRAMECCCHECK_ENABLE  0  /* Move to main() */
#define EFUSETEST_ENABLE          1
#define CCMR5TEST_ENABLE          1
/* USER CODE END */
void handlePLLLockFail(void);
/* Startup Routine */
void _c_int00(void);
#define PLL_RETRIES 5U
/* USER CODE BEGIN (4) */
/* USER CODE END */

#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
#pragma WEAK(_c_int00)

/* SourceId : STARTUP_SourceId_001 */
/* DesignId : STARTUP_DesignId_001 */
/* Requirements : HL_CONQ_STARTUP_SR1 */
void _c_int00(void)
{
	register resetSource_t rstSrc;
/* USER CODE BEGIN (5) */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();

    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */
    rstSrc = getResetSource();

    switch(rstSrc)
    {
        case POWERON_RESET:

        /* Initialize L2RAM to avoid ECC errors right after power on
         * Use NEO's version, because TI's code is shite.
         */
        _memInitNeo_();

        /* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
        {
            /* Put system in a safe state */
            handlePLLLockFail();
        }

#if 0
/* USER CODE END */

    /* Initialize Core Registers to avoid CCM Error */
    _coreInitRegisters_();
	
    /* Initialize Stack Pointers */
    _coreInitStackPointer_();

    /* Reset handler: the following instructions read from the system exception status register
     * to identify the cause of the CPU reset.
     */
	rstSrc = getResetSource();
    switch(rstSrc)
    {
        case POWERON_RESET:
		/* Initialize L2RAM to avoid ECC errors right after power on */
		_memInit_();

		/* Add condition to check whether PLL can be started successfully */
        if (_errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U)
		{
			/* Put system in a safe state */
			handlePLLLockFail();
		}
		
/*SAFETYMCUSW 62 S MR:15.2, 15.5 <APPROVED> "Need to continue to handle POWERON Reset" */
        case DEBUG_RESET:
        case EXT_RESET:

/* USER CODE BEGIN (6) */
/* USER CODE END */

        /* Initialize L2RAM to avoid ECC errors right after power on */
		if(rstSrc != POWERON_RESET)
		{
			_memInit_();
		}

/* USER CODE BEGIN (7) */

/* USER CODE END */

/* USER CODE BEGIN (8) */
/* USER CODE END */


/* USER CODE BEGIN (9) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();

/* USER CODE BEGIN (10) */
/* USER CODE END */

        /* Check if there were ESM group3 errors during power-up.
         * These could occur during eFuse auto-load or during reads from flash OTP
         * during power-up. Device operation is not reliable and not recommended
         * in this case. */
        if ((esmREG->SR1[2]) != 0U)
        {
           esmGroup3Notification(esmREG,esmREG->SR1[2]);               
        }
	
        /* Initialize System - Clock, Flash settings with Efuse self check */
        systemInit();

/* USER CODE BEGIN (11) */
#endif

        case EXT_RESET:
        case DEBUG_RESET:
        case SW_RESET:

        if (rstSrc != POWERON_RESET)
        {
            _memInitNeo_();
        }

        _coreEnableEventBusExport_();

        /* Check if there were ESM group3 errors during power-up.
         * These could occur during eFuse auto-load or during reads from flash OTP
         * during power-up. Device operation is not reliable and not recommended
         * in this case. */
        if ((esmREG->SR1[2]) != 0U)
        {
           esmGroup3Notification(esmREG,esmREG->SR1[2]);               
        }

        /* Copy int vectors here to allow exceptions (will need re-copied later after mem tests) */
        copy_in(&ramIntvecsCpyTbl);

        /* Initialize System - Clock, Flash settings with Efuse self check */
        systemInit();

#if (PBIST_ROM_ENABLE == 1) || (PBIST_L2RAM_ENABLE == 1) || (PBIST_PERIPHRAM_ENABLE == 1)

        /* Workaround for the Errata PBIST#4 */
        errata_PBIST_4();
#endif

#if PBIST_ROM_ENABLE == 1
        {
            boolean retVal;

            /* Start PBIST on STC and PBIST ROM */
            retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
                                        PBIST_RAMGROUP_01_PBIST_ROM |
                                        PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
                                        PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
                                        PBIST_RAMGROUP_04_STC2_ROM_NHET,
                                        PBISTALGO_TRIPLE_READ_FAST_READ |
                                        PBISTALGO_TRIPLE_READ_SLOW_READ);
            if(retVal == false){while(1);}
        }
#endif
#if EFUSETEST_ENABLE == 1
        {
            boolean retVal;
            SL_EFuse_Config config;
            uint32 efcStatus;

            config.numPatterns      = 600u;
            config.seedSignature    = 0x5362F97Fu;
            config.failInfo.stResult= ST_FAIL;
            config.failInfo.failInfo= EFUSE_ERROR_NONE;

            efcStatus = efcREG->ERR_STAT;
            if(efcStatus == 0x0U)
            {
                /* Run Stuck At Zero Test (param2=TRUE - Wait for complete) */
                retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_STUCK_AT_ZERO, TRUE, &config);
                if(retVal == false){while(1);}

                if(config.failInfo.stResult == ST_PASS)
                {
                    /* Run efuse self test (param2=TRUE - Wait for complete) */
                    retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_ECC, TRUE, &config);
                    if(retVal == false){while(1);}
                    if(config.failInfo.stResult != ST_PASS)
                    {
                        /* Selftest failed - Class 2 error */
                        while(1);
                    }
                }
                else
                {
                    /* Stuck At Zero test failed - Class 2 error */
                    while(1);
                }
            }
            else
            {
                if (efcStatus == 0x15U)
                {
                    /* Run efuse self test (param2=TRUE - Wait for complete) */
                    retVal = SL_SelfTest_EFuse(EFUSE_SELF_TEST_ECC, TRUE, &config);
                    if(retVal == false){while(1);}
                    if(config.failInfo.stResult != ST_PASS)
                    {
                        /* Selftest failed - Class 2 error */
                        while(1);
                    }
                    else
                    {
                        /* Selftest passed - Class 3 error */
                        while(1);
                    }
                }
                else
                {
                    /* Class 2 error */
                    while(1);
                }
            }
        }
#endif
#if PBIST_ROM_ENABLE == 1
        {
            SL_PBIST_FailInfo pbistStatus;

            /* Wait for PBIST on ROM to complete */
            while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
            SL_SelfTest_PBIST_StopExec();

            if(pbistStatus.stResult != ST_PASS)
            {
                /* PBIST fail */
                while(1);
            }

            /* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
            vimREG->INTREQ2 = 0x00200000;
        }
#endif
#if PBIST_L2RAM_ENABLE == 1
        {
            /* Run PBIST on L2RAM */
            SL_SelfTest_PBIST( PBIST_EXECUTE,
                                        PBIST_RAMGROUP_29_L2RAMW |
                                        PBIST_RAMGROUP_30_L2RAMW,
                                        PBISTALGO_MARCH13N_1PORT);

            while((systemREG1->MSTCGSTAT & 0x1u) == 0x0u);

            if ((pbistREG->FSRF0 == 0u) && (pbistREG->FSRF1 == 0u))
            {
                /* PBIST pass */
            }
            else
            {
                /* PBIST fail */
                while(1);
            }

            SL_SelfTest_PBIST_StopExec();
            _memInitNeo_();

            /* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
            vimREG->INTREQ2 = 0x00200000;
        }
#endif

#if PBIST_PERIPHRAM_ENABLE == 1
        {
            boolean retVal;

            /* Run PBIST on dual port memories (except VIM) */
            retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
                                        PBIST_RAMGROUP_05_AWM1                |
                                        PBIST_RAMGROUP_06_DCAN1               |
                                        PBIST_RAMGROUP_07_DCAN2               |
                                        PBIST_RAMGROUP_08_DMA                 |
                                        //PBIST_RAMGROUP_09_HTU1                |
                                        PBIST_RAMGROUP_10_MIBSPI1             |
                                        PBIST_RAMGROUP_11_MIBSPI2             |
                                        PBIST_RAMGROUP_12_MIBSPI3             |
                                        PBIST_RAMGROUP_13_NHET1               |
                                        PBIST_RAMGROUP_16_RTP                 |
                                        PBIST_RAMGROUP_18_AWM2                |
                                        PBIST_RAMGROUP_19_DCAN3               |
                                        PBIST_RAMGROUP_20_DCAN4               |
                                        //PBIST_RAMGROUP_21_HTU2                |
                                        PBIST_RAMGROUP_22_MIBSPI4             |
                                        PBIST_RAMGROUP_23_MIBSPI5             |
                                        PBIST_RAMGROUP_24_NHET2,
                                        //PBIST_RAMGROUP_25_FTU                 | /* Enable only in TMS device */
                                        //PBIST_RAMGROUP_26_FRAY_INBUF_OUTBUF   | /* Enable only in TMS device */
                                        //PBIST_RAMGROUP_27_CPGMAC_STATE_RXADDR | /* Ethernet */
                                        //PBIST_RAMGROUP_28_CPGMAC_STAT_FIFO /* Ethernet */
                                        PBISTALGO_MARCH13N_2PORT);
            if(retVal == false){while(1);}
        }
#endif
#if L2RAMECCCHECK_ENABLE == 1
        {
            boolean retVal;
            SL_SelfTest_Result result;

            retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &result);
            if(retVal == false){while(1);}
            if(result != ST_PASS)
            {
                /* Test fail */
                while(1);
            }

            retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &result);
            if(retVal == false){while(1);}
            if(result != ST_PASS)
            {
                /* Test fail */
                while(1);
            }

        }
#endif
#if FLASHECCCHECK_ENABLE == 1
        {
            boolean retVal;
            SL_SelfTest_Result result;

            /* Flash test needs to be run from a RAM location. Copy flash test to RAM */
            uint32 i;
            uint32 size=(uint32)&ulHighHandlerSize;
            for(i=0;i<size;i++)
            {
                ((char *)&ulHighHandlerStartAddr)[i] =((char *)&ulHighHandlerLoadStart)[i];
            }

            retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_1BIT, TRUE, &result);
            if(retVal == false){while(1);}
            if(result != ST_PASS)
            {
                /* Test fail */
                while(1);
            }

            retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &result);
            if(retVal == false){while(1);}
            if(result != ST_PASS)
            {
                /* Test fail */
                while(1);
            }
        }
#endif
#if PBIST_PERIPHRAM_ENABLE == 1
        {
            SL_PBIST_FailInfo pbistStatus;

            while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
            SL_SelfTest_PBIST_StopExec();

            if(pbistStatus.stResult != ST_PASS)
            {
                /* PBIST fail */
                while(1);
            }

            /* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
            vimREG->INTREQ2 = 0x00200000;

            /* Memory Init for MIBSPI */
            mibspiREG1->GCR0 = 0x1U;
            mibspiREG2->GCR0 = 0x1U;
            mibspiREG3->GCR0 = 0x1U;
            mibspiREG4->GCR0 = 0x1U;
            mibspiREG5->GCR0 = 0x1U;

            while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
            {
            }/* Wait */
            mibspiREG1->MIBSPIE = 1;
            mibspiREG1->PAR_ECC_CTRL = (mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;

            while ((mibspiREG2->FLG & 0x01000000U) == 0x01000000U)
            {
            }/* Wait */
            mibspiREG2->MIBSPIE = 1;
            mibspiREG2->PAR_ECC_CTRL = (mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;

            while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
            {
            }/* Wait */
            mibspiREG3->MIBSPIE = 1;
            mibspiREG3->PAR_ECC_CTRL = (mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;

            while ((mibspiREG4->FLG & 0x01000000U) == 0x01000000U)
            {
            }/* Wait */
            mibspiREG4->MIBSPIE = 1;
            mibspiREG4->PAR_ECC_CTRL = (mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;

            while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
            {
            }/* Wait */
            mibspiREG5->MIBSPIE = 1;
            mibspiREG5->PAR_ECC_CTRL = (mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0) | 0xA;

            /* Enable ECC for other RAMs */
            dmaREG->DMAPCR = 0xA;
            hetREG1->PCR   = 0xA;
            htuREG1->PCR   = 0xA;
            hetREG2->PCR   = 0xA;
            htuREG2->PCR   = 0xA;
            canREG1->CTL   = (canREG1->CTL & 0xFFFFC3FF) | (0xA << 10);
            canREG2->CTL   = (canREG2->CTL & 0xFFFFC3FF) | (0xA << 10);
            canREG3->CTL   = (canREG3->CTL & 0xFFFFC3FF) | (0xA << 10);
            canREG4->CTL   = (canREG4->CTL & 0xFFFFC3FF) | (0xA << 10);
            /* Initialize CAN module before using it */
            canREG1->CTL &= ~(uint32)(0x00000041U);
            canREG2->CTL &= ~(uint32)(0x00000041U);
            canREG3->CTL &= ~(uint32)(0x00000041U);
            canREG4->CTL &= ~(uint32)(0x00000041U);
            adcREG1->PARCR = 0xA;
            adcREG2->PARCR = 0xA;

            /* Memory Init for all RAMs (except VIM) with correct ECC */
            SL_Init_Memory( RAMTYPE_DMA_RAM     |
                            RAMTYPE_NHET1       |
                            RAMTYPE_HET_TU1     |
                            RAMTYPE_NHET2       |
                            RAMTYPE_HET_TU2     |
                            RAMTYPE_DCAN1_RAM   |
                            RAMTYPE_DCAN2_RAM   |
                            RAMTYPE_DCAN3_RAM   |
                            RAMTYPE_DCAN4_RAM   |
                            RAMTYPE_MIBSPI1_RAM |
                            RAMTYPE_MIBSPI2_RAM |
                            RAMTYPE_MIBSPI3_RAM |
                            RAMTYPE_MIBSPI4_RAM |
                            RAMTYPE_MIBSPI5_RAM |
                            RAMTYPE_MIBADC1_RAM |
                            RAMTYPE_MIBADC2_RAM );
        }
#endif
#if PERIPHRAMECCCHECK_ENABLE == 1
        {

            canInit();
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN1) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN1) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN2) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN2) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN3) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN3) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_1BIT, SL_DCAN4) == false)
            {
                while(1);
            }
            if(SL_SelfTest_CAN(CAN_ECC_TEST_MODE_2BIT, SL_DCAN4) == false)
            {
                while(1);
            }
            if(SL_SelfTest_DMA(DMA_ECC_TEST_MODE_1BIT) == false)
            {
                while(1);
            }
            if(SL_SelfTest_DMA(DMA_ECC_TEST_MODE_2BIT) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI1) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI1) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI2) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI2) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI3) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI3) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI4) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI4) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_1BIT, SL_MIBSPI5) == false)
            {
                while(1);
            }
            if(SL_SelfTest_MibSPI(MIBSPI_ECC_TEST_MODE_2BIT, SL_MIBSPI5) == false)
            {
                while(1);
            }
        }
#endif
#if CCMR5TEST_ENABLE == 1
        {
            boolean retVal;
            SL_CCMR5F_FailInfo failInfo;

            retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_CPUCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_VIMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_PDCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_SELF_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_ERROR_FORCING_TEST, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }

            retVal = SL_SelfTest_CCMR5F(CCMR5F_INMCOMP_SELF_TEST_ERROR_FORCING, TRUE, &failInfo);
            if(retVal == false){while(1);}
            if(failInfo.stResult != ST_PASS)
            {
                while(1);
            }
        }
#endif
#if PBIST_VIM_ENABLE == 1
        {
            boolean retVal;
            SL_PBIST_FailInfo pbistStatus;

            /* Start PBIST on STC and PBIST ROM */
            retVal = SL_SelfTest_PBIST( PBIST_EXECUTE,
                                        PBIST_RAMGROUP_01_PBIST_ROM |
                                        PBIST_RAMGROUP_02_STC1_1_ROM_R5 |
                                        PBIST_RAMGROUP_03_STC1_2_ROM_R5 |
                                        PBIST_RAMGROUP_04_STC2_ROM_NHET,
                                        PBISTALGO_TRIPLE_READ_FAST_READ |
                                        PBISTALGO_TRIPLE_READ_SLOW_READ);
            if(retVal == false){while(1);}

            /* Wait for PBIST on ROM to complete */
            while(SL_SelfTest_Status_PBIST(&pbistStatus) == FALSE);
            SL_SelfTest_PBIST_StopExec();

            if(pbistStatus.stResult != ST_PASS)
            {
                /* PBIST fail */
                while(1);
            }

            /* Clear VIM pending interrupt request (Channel 85 - PBIST Done) */
            vimREG->INTREQ2 = 0x00200000;
        }
#endif

/* USER CODE END */

        /* Enable IRQ offset via Vic controller */
        _coreEnableIrqVicOffset_();
            
        /* Initialize VIM table */
	    vimInit();

/* USER CODE BEGIN (12) */
/* USER CODE END */
        /* Configure system response to error conditions signaled to the ESM group1 */
        /* This function can be configured from the ESM tab of HALCoGen */
        esmInit();

/* USER CODE BEGIN (13) */

        /* Copy the ram exception vector jump table */
        copy_in(&ramIntvecsCpyTbl);

        /* Init safety lib ESM AFTER esmInit() */
        SL_ESM_Init(&ESM_ApplicationCallback);

        /* and start handling (the ESM) FIQ */
        _enable_interrupt_();

#if STC_ENABLE == 1
        if(DEBUG_RESET != rstSrc)
        {
            SL_STC_Config stcSelfTestConfig;

            stcSelfTestConfig.stcClockDiv        = 0;             /* STC Clock divider = 1 */
            stcSelfTestConfig.intervalCount     = 1;             /* One interval only */
            stcSelfTestConfig.restartInterval0     = TRUE;         /* Start from interval 0 */
            stcSelfTestConfig.timeoutCounter     = 0xFFFFFFFF;     /* Timeout counter*/

            _SL_HoldNClear_nError();

            SL_SelfTest_STC(STC1_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
            while(1); /* STC failed to start */
        }
#endif
/* USER CODE END */

        break;

        case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
        break;
		
        case WATCHDOG_RESET:
        case WATCHDOG2_RESET:
				
/* USER CODE BEGIN (15) */
/* USER CODE END */
        break;
    
        case CPU0_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */

/* USER CODE BEGIN (17) */
/* USER CODE END */
		
/* USER CODE BEGIN (18) */
/* USER CODE END */

        /* Enable CPU Event Export */
        /* This allows the CPU to signal any single-bit or double-bit errors detected
         * by its ECC logic for accesses to program flash or data RAM.
         */
        _coreEnableEventBusExport_();
		
/* USER CODE BEGIN (19) */
#if STC_ENABLE == 1

        if ((stcREG1->STCSCSCR & 0xFU) == 0xAU)
        {
            /* check if the self-test fail bit is set */
            if ((stcREG1->STCGSTAT & 0x3U) != 0x3U)
            {
                /* STC self-check has failed */
                while(1);
            }
            /* STC self-check has passed */
            else
            {
                /* clear self-check mode */
                stcREG1->STCSCSCR = 0x05U;

                /* clear STC global status flags */
                stcREG1->STCGSTAT = 0x3U;

                /* clear ESM group1 channel 27 status flag */
                esmREG->SR1[0U] = 0x08000000U;
                {
                    SL_STC_Config stcSelfTestConfig;
                    stcSelfTestConfig.stcClockDiv        = 0;             /* STC Clock divider = 1 */
                    stcSelfTestConfig.intervalCount      = 1;             /* One interval only */
                    stcSelfTestConfig.restartInterval0   = TRUE;         /* Start from interval 0 */
                    stcSelfTestConfig.timeoutCounter     = 0xFFFFFFFF;     /* Timeout counter*/

                    _SL_HoldNClear_nError();

                    SL_SelfTest_STC(STC1_RUN, TRUE, &stcSelfTestConfig);
                    while(1); /* STC failed to start */
                }
            }
        }
        /* CPU reset caused by CPU self-test completion */
        else if ((stcREG1->STCGSTAT & 0x1U) == 0x1U)
        {
            /* Self-Test Fail flag is set */
            if ((stcREG1->STCGSTAT & 0x2U) == 0x2U)
            {
                /* Call CPU self-test failure handler */
                while(1);
            }
            /* CPU self-test completed successfully */
            else
            {
                /* clear STC global status flag */
                stcREG1->STCGSTAT = 0x1U;

                /* Continue start-up sequence after CPU STC completed */
            }
        }
        /* CPU reset caused by software writing to CPU RESET bit */
        else
        {
            /* Add custom routine here to handle the case where software causes CPU reset */
        }
#endif
#if 0
/* USER CODE END */
        break;
    
        case SW_RESET:
		
/* USER CODE BEGIN (20) */
#endif
/* USER CODE END */
        break;
    
        default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
        break;
    }

/* USER CODE BEGIN (22) */

    /* Copy flash writing code into RAM */
    copy_in(&flashCpyTbl);

/* USER CODE END */

    _mpuInit_();
	
/* USER CODE BEGIN (23) */
/* USER CODE END */

    _cacheEnable_();

/* USER CODE BEGIN (24) */
/* USER CODE END */


/* USER CODE BEGIN (25) */
/* USER CODE END */

        /* initialize global variable and constructors */
    __TI_auto_init();
/* USER CODE BEGIN (26) */

    _enable_interrupt_();

/* USER CODE END */
    
        /* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
    main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
    exit(0);


/* USER CODE BEGIN (28) */
/* USER CODE END */

}

/* USER CODE BEGIN (29) */
/* USER CODE END */

/** @fn void handlePLLLockFail(void)
*   @brief This function handles PLL lock fail.
*/
/* USER CODE BEGIN (30) */
/* USER CODE END */
void handlePLLLockFail(void)
{
/* USER CODE BEGIN (31) */
/* USER CODE END */
	while(1)
	{
		
	}
/* USER CODE BEGIN (32) */
/* USER CODE END */
}
/* USER CODE BEGIN (33) */
/* USER CODE END */

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: EMS 2.3 Bus Error on Devboard, but not on custom board

Root Cause - Likely Debugger Flash Programming Difference

Key Issues to Address:

Recommended Solutions:

Additional Checks:

Debugging Steps:

Interrupts Not Firing When Self-Tests Are Enabled

Debug vs Release Build Differences