TMS570LC4357: HALCoGen 04.07.01: eQEP register offset mismatch vs TRM (TMS570LC4357)

Hi Danilo,

I can confirm that these register addresses are swapped. Per the TMS570LC43x TRM (SPNU563A), the documented offsets are:

• QCTMR — offset 0x38 (16-bit capture timer, provides time base for edge capture unit) [1]
• QEPSTS — offset 0x3A (status register containing flags such as COEF, which indicates QCTMR overflow) [2]

These are confirmed in both the eQEP memory map table and the individual register description sections of the TRM [3].

I reviewed the published HALCoGen bug list [4] and the Hercules documentation bug list [5] for the TMS570LC4357. Neither list documents a QCTMR/QEPSTS register offset swap. The HALCoGen CSP known issues document (SPNA240) also does not reference any eQEP register offset problem [6].

I will file an internal ticket with the development team to review and determine a possible update timeline.

1. TMS570LC43x TRM - QCTMR Register (SPNU563A, p.1992)
2. TMS570LC43x TRM - QEPSTS Register (SPNU563A, p.1993)
3. TMS570LC43x TRM - eQEP Memory Map (SPNU563A, p.1962)
4. FAQ: List of Bugs in HALCoGen (E2E)
5. FAQ: List of Documentation Bugs in Hercules Devices (E2E)
6. HALCoGen CSP Known Issues (SPNA240)

Best Regards,

Zackary Fleenor