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TMS570 DCAN module parity error interrupt

Chuck Wong
Genius 3940 points

Hey guys,

I'm a bit confused in the understanding of the TMS570 DCAN module parity error generation mechanism. Please shed some light ...

In one hand, DCAN1 as an example, there is a "DCAN1 - parity" error source under ESM Group 1 at channel 21 that I can read within the VIM as "ESM High level interrupt (VMI)" as request 0. I can apparently enable this error source to generate interrupt by setting appropriate bit inside the ESMIESR1 register. Where can I turn ON the parity function of this parity check? PMD bits in the DCAN1CTRL register?

In other hand, there is also a "Parity Error" that can be enabled by configuring the DCAN1CTL register within the DCAN module, error which will pass-thru to the VIM as "DCAN1 level 0 interrupt" as request 16. I should enable this error generation by enabling PMD (parity function enable), EIE (error interrupt enable) and IE0 (interrupt line 0 enable) of the DCAN1CTL register. (right?)

So my question is: Which is which?

Thanks for any help.

Regards,

Chuck.

  • 0
    TI__Intellectual 1400 points

    Hi Chuck,

         Thank you for your support of our forum. I'll check for the answer of your question and reply to you later.

    Thanks and Best Regards,

    Ken

  • 0
    TI__Mastermind 22715 points

    Chuck,

    The parity check function is enabled by setting the PMD field in the DCANxCTL to a non-0x5 value. A parity error will sets the PER bit in the DCAN status register.

    If the EIE and and IE0 bits are set, PER flag will cause a DCAN interrupt. User can read the DCAN status register to find the cause. PER flag is also connected to the ESM module. If you enable this input in ESM by configuring the ESM register, it can also cause an ESM interrupt. You can also program ESM so that this error will force the error pin to low.

    Please let know if this answers your question.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3940 points

    Thanks Zhaohong,

    That answered my question. I can see that passing through the ESM can additionally activate the Error Pin, if desired. This should be the same logic that applies to SPI, ADC etc.

    I have however another question. After enabling the DCAN parity ESM interrupt for both DCAN1 and DCAN2, then use the following sequence to enable parity check, I got intermittent DCAN1 Parity error ESM interrupt right after power-up, intermittent, not all the time.

    1. Configure VIM
    2. Configure ESM
    3. Enable DCAN parity check (PMD) using bits writing, i.e. every line physically write to the DCANAxCTL registers:

     

        // configure both CAN interfaces (identical function - for redundancy)

        DCAN1CTL_bit.Init = DCAN2CTL_bit.Init = 1;
        DCAN1CTL_bit.CCE  = DCAN2CTL_bit.CCE  = 1;

        while (!DCAN1CTL_bit.Init || !DCAN1CTL_bit.Init)
            continue;

        DCAN1BTR  = DCAN2BTR  = 0x00003AC5;
        DCAN1TIOC = DCAN2TIOC = 0x00000008;
        DCAN1RIOC = DCAN2RIOC = 0x00000008;

        DCAN1CTL_bit.ABO  = DCAN2CTL_bit.ABO  = 1;
        DCAN1CTL_bit.PMD  = DCAN2CTL_bit.PMD  = 0xA;
        DCAN1CTL_bit.CCE  = DCAN2CTL_bit.CCE  = 0;
        DCAN1CTL_bit.Init = DCAN2CTL_bit.Init = 0;

        while (DCAN1CTL_bit.Init || DCAN2CTL_bit.Init)
            continue;

        DCAN1ABOTR = DCAN2ABOTR = 4000000;

     

    I don't believe that I have a faulty MCU. Any clue on my problem?

    Regards,

    Chuck.

  • 0 in reply to Chuck Wong
    TI__Mastermind 22715 points

    Chuck,

    You need to do DCAN RAM initialization using the system module to make DCAN RAM content match with parity.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3940 points

    I let the MCU performs Single Port RAM March13N_red test on both DCAN1 and DCAN2, just before configuring VIM and ESM in my stated sequence.

    I've also set PBIST_OVER bit to 1 to enable RAM override during test.

    No error was detected during PBIST. Passed everytime.