RE: Startup Code for TMS570LS20x - PBIST and RAM init

Hello Mark,

First, it is important to understand that PBIST and Memory auto initialization are 2 separate functions/features. The bit mappings to have a RAM area included in the autoinit function are given in table 2-7 in spns141f. The RAM select value given in the right most column corresponds to the bit position in the MSINENA register as you have mentioned and as shown in the bit mapping table below.

 For the value of 0x657F that you see generated by Halcogen, this corresponds to the RAM selects highighted in the table above being included in the autoinit or HW init of RAM feature. Basically everything except the MibSPI modules and FlexRay RAM (this one is handled automatically by the FlexRay IP).

For PBIST, the corresponding bits in the MSIENA register must be set prior to enableing self-test mode. The following clarification was added to a later TRM for another device (SPNU499b) that uses the same PBIST HW which describes why this must be done:

"In memory self-test mode, all the corresponding bits of the memories to be tested should be set before enabling the global memory selftest controller key (MSTGENA) in the MSTGCR register (offset 58h). The reason for this is that MSTGENA, in addition to being the global enable for all individual PBIST controllers, is the source for the reset generation to all the PBIST controller state machines. Disabling the MSTGENA or MINITGENA key (by writing from a Ah to any other value) will reset all the MSIENA[31-0] bits to their default values."

For the selection of which RAM groups to actually run the self-test on, you would write the corresponding RAM group bits in the RINFOL and RINFOU. Note that the RAM goups assignments for PBIST are given in table 6-1 in the TRM spnu489c which are deifferent than the RAM select bit assignments because PBIST includes additional test capability for the PBIST ROM areas. Also note that the RAM Group numbering is 1 based which means that RAM GROUP1 maps to bit0 in the RINFOL register.

There are some examples for PBIST describing the steps to go through in sections 6.8. I do see 1 descrepancy in these examples where they always write a 1 to the MSIENA register selection bits instead of each selected RAM Group. This is due to the fact that selecting just one of the RAM groups in the MSIENA register will, in fact, cause all PBIST group controllers to reset so there really is no need to select all groups in the MSIENA register as there isn't really a relationship between the RAM select bits and the RAM Group selection via RINFOx registers.

Finally, to address your question about the MibSPI reset status and the impact on PBIST/MEMINIT. If you are going to utilize the Mib RAM then the modules should be out of reset when you complete the RAM init and PBIST for these groups. If you will not be using the MibRAM, then it isn't neccessary to do anything to them. From a safety perspective certification perspective, it might be needed to prove non-interferance from these RAM areas so you may want to setup the MPU to prevent access to them by your code.

Sorry for the long drawn out answer. I hope this helps clear up any confusion for you.