Using the "Blinky_Example" a modified example RM42L432 and TMX570LS0432 (Launchpad is two Hercules) are dead. Ie they can not be reprogrammed, even using an external emulator (j-link IAR KS). The modified code is part of the file "\ Blinky_Example \ source \ system.c":
void setupPLL(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** - Configure PLL control registers */
/** @b Initialize @b Pll1: */
/** - Setup pll control register 1:
* - Setup reset on oscillator slip
* - Setup bypass on pll slip
* - setup Pll output clock divider to max before Lock
* - Setup reset on oscillator fail
* - Setup reference clock divider
* - Setup Pll multiplier
*/
/* systemREG1->PLLCTL1 = 0x00000000U
| 0x20000000U
| ((0x1F)<< 24U)
| 0x00000000U
| ((6U - 1U)<< 16U)
| ((120U - 1U)<< 8U);
*/
systemREG1->PLLCTL1 = 0x21046300; //80MHz
/** - Setup pll control register 2
* - Enable/Disable frequency modulation
* - Setup spreading rate
* - Setup bandwidth adjustment
* - Setup internal Pll output divider
* - Setup spreading amount
*/
/* systemREG1->PLLCTL2 = 0x00000000U
| (255U << 22U)
| (7U << 12U)
| ((2U - 1U)<< 9U)
| 61U;
*/
systemREG1->PLLCTL2 = 0x3FC0723D; //80MHz
/** @b Initialize @b Pll2: */
/** - Setup pll2 control register :
* - setup Pll output clock divider to max before Lock
* - Setup reference clock divider
* - Setup internal Pll output divider
* - Setup Pll multiplier
*/
systemREG2->PLLCTL3 = ((2U - 1U) << 29U)
| ((0x1F)<< 24U)
| ((6U - 1U)<< 16U)
| ((120U - 1U) << 8U);
/** - Enable PLL(s) to start up or Lock */
systemREG1->CSDIS = 0x00000000U
| 0x00000000U
| 0x00000008U
| 0x00000080U
| 0x00000000U
| 0x00000000U
| 0x00000000U;
systemREG1->CSDISCLR = 0x00000002U; // Enable clock source 1
systemREG1->CSDIS |= 0xf9u;
}
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** - Configure PLL control registers */
/** @b Initialize @b Pll1: */
/** - Setup pll control register 1:
* - Setup reset on oscillator slip
* - Setup bypass on pll slip
* - setup Pll output clock divider to max before Lock
* - Setup reset on oscillator fail
* - Setup reference clock divider
* - Setup Pll multiplier
*/
/* systemREG1->PLLCTL1 = 0x00000000U
| 0x20000000U
| ((0x1F)<< 24U)
| 0x00000000U
| ((6U - 1U)<< 16U)
| ((120U - 1U)<< 8U);
*/
systemREG1->PLLCTL1 = 0x21046300; //80MHz
/** - Setup pll control register 2
* - Enable/Disable frequency modulation
* - Setup spreading rate
* - Setup bandwidth adjustment
* - Setup internal Pll output divider
* - Setup spreading amount
*/
/* systemREG1->PLLCTL2 = 0x00000000U
| (255U << 22U)
| (7U << 12U)
| ((2U - 1U)<< 9U)
| 61U;
*/
systemREG1->PLLCTL2 = 0x3FC0723D; //80MHz
/** @b Initialize @b Pll2: */
/** - Setup pll2 control register :
* - setup Pll output clock divider to max before Lock
* - Setup reference clock divider
* - Setup internal Pll output divider
* - Setup Pll multiplier
*/
systemREG2->PLLCTL3 = ((2U - 1U) << 29U)
| ((0x1F)<< 24U)
| ((6U - 1U)<< 16U)
| ((120U - 1U) << 8U);
/** - Enable PLL(s) to start up or Lock */
systemREG1->CSDIS = 0x00000000U
| 0x00000000U
| 0x00000008U
| 0x00000080U
| 0x00000000U
| 0x00000000U
| 0x00000000U;
systemREG1->CSDISCLR = 0x00000002U; // Enable clock source 1
systemREG1->CSDIS |= 0xf9u;
}
JTAG signals are present, as the oscillator. nERROR remains high all the time. Obviously the program is not running.
When this program "failed" was charged nERROR was observed that low for a few seconds, and then death.
When this program "failed" was charged nERROR was observed that low for a few seconds, and then death.
Thanks
