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TMS570 Data/Prefetch abort sources

Henry Abril1
Intellectual 485 points

Hi,

a. AFAIK the following ESM sources (1, 2, 3 & 4) are generating DATA ABORT only(not prefetch abort), is that correct?

1. ESM Group3 - Channel 1: eFuse Controller - autoload error

2. ESM Group3 - Channel 3: RAM even bank (B0TCM) - ECC uncorrectable error

3. ESM Group3 - Channel 5: RAM even bank (B1TCM) - ECC uncorrectable error

4. ESM Group3 - Channel 7: FMC - uncorrectable error: bus1 and bus2 interfaces

b. Could you please help me to clarify which kind of abort is generated by the sources/conditions detailed below:

SPNU499B November 2012–Revised August 2013

2.3.2.5 Conditions That Generate Aborts
An Abort is generated under the following conditions on the TMS570LS31x/21x microcontrollers.
• Access to an illegal address (a nonimplemented address) (data abort? Prefetch abort?)
• Access to a protected address (protection violation) (data abort? Prefetch abort?)
• Parity / ECC / Time-out Error on a valid access (data abort? Prefetch abort?)

Addresses Protected By MPU: (data abort? Prefetch abort?)
Protection of Peripheral Register and Memory Frames: (data abort? Prefetch abort?)

Thank you,

 

  • 0
    TI__Mastermind 49120 points

    Henry,

    An abort is the CPU's response to an error on a transaction that it initiates.

    An error on an instruction fetch (or rather prefetch) causes a prefetch abort if that instruction actually gets to the "execute" phase. The Cortex-R4F features a speculative fetch wherein it tries to maximize the instruction fetch bandwidth by prefetching from the program memory space. Not all these prefetches are used and do not cause an abort even if some of the prefetches may cause an error.

    Similarly an error on a data fetch causes a data abort.

    Most applications use the main flash memory as the program memory and the TCM RAM as data memory. In this case, a prefetch abort can only be expected when the CPU tries to fetch an instruction from a flash location that is either not valid (past the available flash memory) or which returns an ECC code that indicates a 2-bit error. You could also use the MPU to define some valid flash region as non-executable memory. A prefetch from such a region will also cause a prefetch abort.

    Hope this helps.

    Regards,

    Sunil

  • 0
    TI__Guru**** 191356 points

    Hello Henry,

      My asnwers are inline.

    1. ESM Group3 - Channel 1: eFuse Controller - autoload error

    CT>> No abort. This is a severe error with the efuse which contains the trim values for the flash.

    2. ESM Group3 - Channel 3: RAM even bank (B0TCM) - ECC uncorrectable error

    CT>> It depends if you execute code out of RAM. If you do, then the code fetch from the RAM which contains ECC uncorrectable error will create prefetch abort. Otherwise, data access from RAM which results in ECC uncorrectable error will create data abort.

    3. ESM Group3 - Channel 5: RAM even bank (B1TCM) - ECC uncorrectable error

    CT>> Same as above.

    4. ESM Group3 - Channel 7: FMC - uncorrectable error: bus1 and bus2 interfaces

    CT>> For Bus1 the abort can be either prefetch or data abort. When you have a literal pool read from the flash, it will create a data abort if it has an uncorrectable ECC error. Otherwise, code fetch from flash will result in prefetch abort if it is an uncorrectable ECC error. For Bus2, the ECC error is detected by the flash wrapper itself when accessing OTP space and ECC space. There is no abort. Only error is sent to the ESM. nERROR pin is asserted.

    b. Could you please help me to clarify which kind of abort is generated by the sources/conditions detailed below:

    SPNU499B November 2012–Revised August 2013

    2.3.2.5 Conditions That Generate Aborts
    An Abort is generated under the following conditions on the TMS570LS31x/21x microcontrollers.
    • Access to an illegal address (a nonimplemented address) (data abort? Prefetch abort?)

    CT>> Again it depends on if the CPU is fetching code or reading data from the illegal address. If it is a code fetch then it is a prefetch abort. If it is a data read, then it is a data abort. Bear in mind that if it is a speculative fetch which is later NOT taken by the CPU then there is no abort.


    • Access to a protected address (protection violation) (data abort? Prefetch abort?)

    CT>> Are you talking about the protection on the peripherals using the protection registers in the PCR module. It will be data abort if you violate the protection configured in the PCR for the modules because you will only do data read from the peripherals.


    • Parity / ECC / Time-out Error on a valid access (data abort? Prefetch abort?)

    CT>> Normally parity/ECC errors on the peripherals are signalled to the ESM. No abort but rather an interrupt to the CPU if you enable the errors in the ESM module to generate generate interrupt. Peripheral ECC/Parity errors are routed to ESM GP1.

    Addresses Protected By MPU: (data abort? Prefetch abort?)

    CT>> If an instruction fetch faults it generates a Prefetch Abort exception. if an explicit memory access faults it generates a Data Abort exception.


    Protection of Peripheral Register and Memory Frames: (data abort? Prefetch abort?)

    CT>> If this is a protection violation due to the peripheral protection configured in the PCR then it is a data abort. If this is a protection violation to a individual register, i.e. writing to a register in user mode when the register is privilege mode protected then normally the write is just ignored. No abort. Reading is always allowed to registers in either user or privilege mode.