Hi,
TMS570LS20206SPGE, Toolset V4.7.1, CCS 4.1.2.00027
I have a very strange problem which I have spent a couple of days trying to resolve but have failed. I have managed to narrow down the symptoms but not the cause.
Overview
My application performs as expected when run under the debug IDE via XDS510USB JTAG under CCS4 on the TMS570 MCU Development Kit (Keil sourced).
When run with no JTAG connection from power-on (by connecting 12V supply), the application continually resets every 1ms until I induce either a warm reset or power-on reset (by buttons on the MCBTMS570 board, this does not cut 12V supply voltage). Thereon, the application performs as expected (no resets).
Symptoms
The reset occurs due to ABORT (PREFETCH) interrupt (I record a flag in RAM on this exception which I am able to inspect on subsequent re-connection of the IDE debug).
The 1ms reset rate corresponds to my RTI 1ms IRQ interrupt task (adjusting the rate of this interrupt directly affects the reset rate).
I have saved the link register (R14) contents into RAM on occurrence of this exception but am not convinced that the values are correct (being for example 0x007D0100, 0xC47D0100, 0x007DA300 and 0xD77D0100).
Affecting Conditions
I have three module interrupt 'groups' defined which appear to induce this problem. The reset occurs if I have all three groups' interrupts configured via VIM (one or more IRQs for the following groups; GIO (my DIO), RTI (my GPT) and SPI). If I disable the interrupts for any one of these groups then the reset no longer occurs.
Checked
I have checked that my IRQ stack is big enough as the affecting conditions might indicate such a problem.
I have made one of the interrupt groups FIQs instead of IRQs to no affect.
Thoughts
I wonder if some initialisation is not occurring properly because wait states are needed. This might explain why the application runs without exception under IDE debug and following a warm reset or power-on reset with no supply removed so that TMS570 RAM, registers etc are retained.
I wonder if the Abort Registers SPSR_ABT, R13_ABT and R14_ABT provide useful information (i.e. the SP and LR at the time of the exception abort) or are they related to some other abort condition.
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I have a CCS4 project available which I can email to a TI employee under our existing NDA.
Regards, Tony.