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Avoiding phantom interrupt when doing VIM FIQ masking

Michael Sch,
Intellectual 800 points
Other Parts Discussed in Thread: TMS570LS3137

Hey guys,

in our System, which is built on top of the TMS570LS3137, we have configured several IRQs and exactly 2 FIQs (except ESM HL).

In some certain cases, we need to disable the two FIQs temporarily when operations on shared data are ongoing. We are doing this by writing the two related bits in the VIMs appropriate REQENACLR register. When reactivating the two FIQs, we're doing this by writing to the REQENASET register. Most of the time this works perfectly fine.

Rather infrequently it happens, that a phantom interrupt is being asserted while the previous context is standing right behind the instruction that performs the disabling of the FIQs. In my opinion, any of the FIQs gets pending right at the same point in time when the STR instruction to the VIM REQENACLR register is being performed.

I already had a look at www.ti.com/.../spna063.pdf.
I think that this is very related to our issue.

The problem is just, that we cannot use the suggested solution since the FIQs cannot be disabled globally. This was the reason why we decided to mask them via the VIM.

Do you know any good solution, on how to temporarily disable FIQs without the need to deal with possible phantom interrupt assertions?
Do we also need to take the peripheral into account when doing this temporal masking?

Thanks in advance.

Kind regards,
Michael

  • 0
    TI__Mastermind 22715 points
    Michael,

    I am guessing that Legacy mode (CPU reads the interrupt offset register) to serve FIQ. The interrupt offset register will not be updated if the mask is turned off. Would you please try software vector mode to serve FIQ?

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Intellectual 800 points
    Hi Zhaohong,

    thanks for the quick response.
    Unfortunately this did not solve our problem.

    From time to time it still happens that a phantom interrupt is being reported at roughly the same time as the VIM masks for the 2 FIQs are being cleared.

    Any ideas?

    Regards,
    Michael
  • 0 in reply to Michael Sch,
    TI__Mastermind 22715 points
    Michael,

    The issue here is that a FIQ request arrives just before the STR instruction to clear the interrupt mask takes effect. As I explained earlier, the update of the interrupt offset register is gated by the mask. It will not get updated if the mask if cleared. It seems that the FIQVECREG register gets updated when the interrupt is latched (before the mask is cleared) and you may be able to work around this issue using software vector mode. To use the software vector mode, you will need to have instruction " ldr pc,[pc,#-0x1b0] " at address 0x1C. you will also need to put the address of the ISR in the VIM RAM.

    If the above does not work for you, the only work around is to ignore the phantom interrupts. In general, the user has to be very careful in dynamically turning on/off interrupts. If the interrupts come from the on-chip peripherals, it will be better to disable/enable the source instead of playing with the VIM module.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    TI__Expert 6985 points

    Michael,

    The only other way to avoid phantom interrupts in this context I can imagine, is to mask the FIQ lines in FIQ mode.

    This could be achieved by triggering a "special" FIQ via SW, or by switching from another operating mode (SuperVisor or System) into FIQ mode.
    In that case FIQ's are disabled and thus masking should not cause problems in terms of phantom interrupts.

    CPU mode changes can be done with the help of the CPS instruction or SVC handlers.

    Best Regards,
    Christian