Why TM4C1294 GPIO output voltage table show only minimum 2.4v for high level.

Mon ami - does not (one) long rule of thumb state that a "logic-high" should exceed 70% of Vdd?   And - as 2.4 > 0.7 * 3.3 - this vendor has complied.

Yet really - as your long experience w/vendor's ill-fated LM3S - and newer devices must reveal - such a low level output only (ever) results when that output is severely loaded - n'est pas?   As my firm uses ARM MCUs from many vendors - I cannot recall a (reasonably) loaded output descending below 2V9 - thus your focus upon a "minimum" value seems "outside" your usual, "Catalog of horrors."   (we assume your dog was well-behaved today - thus forum falls victim...)

Amen bro!    And we must salute your introduction of a, "so relevant" tag to this (otherwise) barren, tech-filled work-space...

Poster will do well to heed valid advice - perhaps steering away from (past) historical anecdotes (justifying?) such unwise usage...

Ohm's law has received more recital here than in many/most electronic texts...   (surely Robert/this reporter appreciate the review...)

Might a (newer "law") "cb1's law" be admitted?... An MCU is neither a "Kitchen Sink" nor a, "Beast of Burden!"  

Your use - as poster Robert has suggested - of a (proper) buffer/driver IC fully resolves.   (no law mention required) 

TC74LVX4245FS is an 8 channel device - sure to meet your/others requirements...

(imported that part no. from disty - cannot defeat/disable the bold...)

BP101 said:

It seems we all agree the Minimal (E) is all that is given Table 27-2 while the GPIO pin is not illustrated as being loaded by any source or sink current in table 27-7.

??? I can't parse this.

BP101 said:

The nominal expected (H) voltage level should be shown relative to the VDD rail voltage provided at steady state (3v3) regardless of any imaginary current loads.

No

BP101 said:

The table is complete nonsense in terms of Ohms law and electronics theory gives no relative or useful information!

Heh, at one point I could derive Ohm's law from more fundamental principles. Anyway, you could interpret this quite easily using Ohms law but you risk error in doing so.

I think cb1 and I have been operating under a mis-apprehension of the detail in the table. I know I was. It means something different than what you have been saying. It does not say that VoH is the minimum output. It is saying that you should not load the output to lower than this value. It then proceeds to give you the current levels which will at which you may reach that level (i.e. higher current draws risk lowering the voltage below the recommended level). Points for recognizing why this is a concern.

Now this drop will happen due to various drops. There will be a resistive drop in the driving FETs, Perhaps a non-ohmic forward drop (certainly if some of the drive is bipolar rather than FET, also the semiconductor metal bond will have non-linearities), resistive drop in metal traces and bonding wires, there will be leakage to the return line. There are probably other items as well. These will depend on operating voltage and temperature, aging, perhaps humidity.

An Ohm's law interpretation would give a figure but it might mislead you as to the voltage at any given loading. It gives you no insight into the temperature variation which could very well be significant.

What this table does give you is enough information to design a working system. You know that as long as you stay within the load limits you are going to have at least 2V4 as a high output. Further in the sheet it adds restrictions on loading to maintain a 10 year lifetime. So design your system to provide no more than the suggested load (observing the larger collective limits as well) and to accept a minimum voltage of 2V4. Any other design is outside the specifications.

Robert

>What this table does give you is enough information to design a working system. You know that as long as you stay within the load limits you are going to have at least 2V4 as a high output.

That does not guarantee the connecting device feels the same way and may expect 3.0v as a nominal High. A nominal value would give some assurance within a know GPIO VDD rail margin. Otherwise the input device may not behave as expected if running at the threshold of the GPIO output regardless of PAD load current. Very often a CMOS input sources only Micro or Nano amp bias current drawn and not milliamps. This device case for a logic 1 input is 2.9v minimum sources 20ua Max, 10ua typical at 5 volts Vin test so the input sources even less current at 2.9v .

Again table 27-7 doesn't show the nominal Hi voltage at any of the possible PAD currents. The PAD resistance is a given at each current level relative to the GPIO VDD reference. Perhaps a % of VDD is not a reliable method and the 2.4v at some point becomes the nominal then what the device just stops working.

Some % of VDD becomes the rail and insures us the GPIO High output level is a known. The hedging is likely for other reasons. Have seen 2.5v mentioned in this datasheet being the High value not 2.4v. Suppose the Stellaris was the same way will have to check that, although GPIO was 5 volt input tolerant it likely did not reach all the way to VDD in a High output level. CB1 stated earlier 70% of VDD. That is a new one on me but why not nothing else is proven in table 27-7 other than as you have discovered.

BP101 said:

That does not guarantee the connecting device feels the same way

That's your job as the designer. You have to match the output from the micro to the input of the device it's driving.  You have enough information on the micro's output to enable you to do that.

BP101 said:

A nominal value would give some assurance within a know GPIO VDD rail margin

If you read there data table carefully you will see that nominal make no sense.

BP101 said:

Perhaps a % of VDD is not a reliable method and the 2.4v at some point becomes the nominal then what the device just stops working.

You are making it overly complex and confusing yourself. 2V4 is a limit you must avoid.  You avoid it by not over loading the output. The load limit is well defined.

The limits are clear and are all you need for proper design.

BP101 said:

CB1 stated earlier 70% of VDD.

That's not a design rule, it's an guideline of what to expect to see in a specification and a sign post of when outputs are deviating from normal and customary.

Robert

BP101 said:

That does not guarantee the connecting device feels the same way and may expect 3.0v as a nominal High

Mon (krazy making) ami,

It is "your" responsibility to insure that the proper signal levels are supplied to all devices w/in your design.   Economics forces limitations upon the chips - especially as speed rises & die area shrinks.

And - do try to be more accurate when (near) quoting another - my comment was "couched" w/ "rule of thumb" which does not imply, "hard/fast/precise!"  (in other words - "Good for Gov't Work.")

We are working on a 100+ Amp BLDC Motor Controller - and to insure that we meet (all) of the signal level requirements we employ (multiple) of the buffer/driver IC I referenced several posts up.   That IC accepts different voltages upon each of two ports!   It then most (effectively) can deliver (exactly) what the targeted IC requires - level shifting quickly & painlessly between different voltage level devices.   (such IS the buffer/driver IC's "Raison d'etre!")  (we happen to translate between 3V3 signals and 5V0 signals (required by our precision Instrumentation Amps).   In your case you may set each of the two ports to 3V3 levels - thus insuring that (even) an enfeebled TM4C output will yield a "solid" 3V3 at the receiving device!  (or a higher voltage, based upon your setting of "Port 2's voltage level")

Best to "insure compliance" - not so much to "sharp-shoot" hapless vendor's spec!

BP101 said:

the GPIO port can produce a binary High voltage level

Is your (considered) point that a decimal high voltage level proves unacceptable?

As Robert & I have (near endlessly) explained - your shipment has delayed by yet another day as you "over-focus upon the trivia" - rejecting all sound guidance...   Someday you (may) have to make payroll - your present methods/madness may have to give way to reality...

BP101 said:

Engineers should first make sure a circuit works on paper and the theory is some what correct prior to entering hardware prototype testing phase.

And you have enough information to do that. We've pointed it out to you several times.

Let me try a more step by step Socratic approach. It will take several messages but maybe you will find it clear at the end.

What is the maximum possible voltage that will be seen on the output pin?

Admittedly this is not explicit in the documentation but the only assumption you have to make to answer it is that TI does not have a boost circuit on their pin driver.

Robert

BP101 said:

The only way to know this peripheral might work with Tiva TM4C is that it now works with Stellaris 3M at 3v3

Patently & absurdly untrue - mon ami!

Might the pedigree & millions of ICs designed/sold/delivered by this vendor prove (ANOTHER) way to know?   You cannot (seriously) believe that this vendor would produce a "fairly standard/long known" circuit which is not in full compliance w/industry standards - can you?   (yet that appears what you seem to suggest...)

Rather than continuing to "beat" this (already dead) horse - your investment of 20-30 minutes in conducting, "GPIO Output Drive" tests would quickly/convincingly, "free your mind from all doubts!"   Four or five properly chosen resistors - connected between various GPIO pins and ground - would go far to assure you that unless "over-loaded" this vendor's MCUs surely meet "industry standard" output-level specifications!

As you obsess upon vendor "specs" - might your presentation of (your) spec - "HERE, NOW" prove a wondrous "model" for this vendor to follow?

The DVM measures 2.98v-2.99v unloaded TM4C GPIO port pin set On. Just barely makes it under peripherals 2.9Vmin. Launch Pad VDD measures 3.299v. So we seem to now have a 9% margin for error.

Intend to use a 3v3 LDO regulator - TPS73533 and TI datasheet TPS735 is not very clear on the exact output voltage. Wacky AMR section show (Vout = -.3min Vin +.3v Max). The intended input voltage is +5v.
With any luck MPU VDD can be set to exceed 3.3v but keeping well under 3.63v Max Table 27-6.

So we manage to make VDD 3.39v - where is it discussed in TM4C1294NCPDT datasheet the GPIO voltage will follow or adjust the binary High by some % of VDD? Perhaps I have missed this in the text but it would be nice to know that might occur as a result.

That maneuver intends to adjust the GPIO binary High level upward to 3.10v min. thus ensuring a 11% binary margin for any deviations in chip dies about the GPIO mux and or port structures. Might simply amount to a precision resistor change in +5 volt supply FB circuit.

sigh,

Take a look at the data table.  It tells you the guaranteed minimum voltage under the entire range of power supply, temperature and allowable load.

BP101 said:

Intend to use a 3v3 LDO regulator - TPS73533 and TI datasheet TPS735 is not very clear on the exact output voltage. Wacky AMR section show (Vout = -.3min Vin +.3v Max).

That is typical a typical spec sheet, have you never read one before? And why on earth are you designing using the AMR?? Those are stress ratings not operating values.  You design with the electrical characteristics section.

BP101 said:

That maneuver intends to adjust the GPIO binary High level upward to 3.10v min.

You can do that, but you have a properly engineered solution available.  Why are you avoiding it? You are going to a lot of effort to avoid it too.

BP101 said:

So we manage to make VDD 3.39v

I once saw a man cutting aluminium roofing with a chainsaw^*. Some things should be avoided even when possible to do.

Robert

* - Really I did - spiral filings flying everywhere - I'm glad I was on the roof and he was on the ground. It's all fun and games until someone loses an eye. 

Not all manufacturers stress this but I didn't think TI would be one to forgo the boilerplate so from the data sheet, Underlined emphasis mine

TI  

Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.  These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

BP101 said:

Vendors AMR saves the day after all, the Binary low will be no less than 2.6v.

While "self-awarded" Suggested Answers most always prove suspect - yours (here) is Dead Wrong!   (where is the proof-reader?)

You've just stated that a "LOW" will equal or exceed 2V6!   That is not NOW - nor has it ever been the case - for devices running from at/about 3V3!

We note too that despite poster Robert's "best efforts" original poster "clings & then credits" Absolute Maximum Values as, "Holy Grail!"   A re-read of Robert's "import" of "Absolute Maximum Use CAUTIONS" seems very much in order...

And the "sorrow" over the thread's "drag out" rings w/out conviction...

BP101 said:

low will be no less than 2.6v.

You ARE assuredly Dead Wrong!   And all the shape-shifting cannot save you.

Is not - by following your logic (quoted clearly, above) a 3V3 level, "No less than 2.6V?"   Thus - the novel "bp101 ruling" - is that 3V3 MUST be a Logic LOW!

Defending the indefensible is never easy - yet you are moving (some may say, steadily) in that direction - are you not?

I leave the "suggested answer" under protest - no one was suggesting the 3V3 or 3V2 or 3V1 input signal arrived from the 3V3 rail.

According to (soon to be guru) poster bp101 - any such input voltage (2V6 or above) will be judged a Logic LOW - which is clearly DEAD WRONG!

Self-awarded "Suggested or Verified" Answers must be viewed w/great suspicion!

BP101 said:

the Binary low will be no less than 2.6v.

What's to hold on?   Is not your language absolutely clear - as quoted above?

And - as always - it remains DEAD Wrong!  (you're shape-shifting cannot save you!)

Now my concern is for innocent/inexperienced "others" who may wander here - and read "your" Suggested Answer - which is (and remains) DEAD WRONG!

BP101 said:

Do agree in substance AMR serves to protect production yield both vendor and buyer.

No

BP101 said:

Designers have to use discretion and evaluate each AMR line independently

No, designers must not approach the Abs Max ratings.

BP101 said:

Some lines obviously have severe consequences when pushed up against or beyond the documented values shown in the AMR.

ALL

Robert

The AMR is not the death trap you fellows are making it out as. Appears both of you have missed the point the AMR of the peripheral mentioned in this Post specifically relates to the missing GPIO output electrical specification for nominal and maximum. Perhaps should remove the green question answered since it was not exactly on point. The reason for marking it answered was the AMR of the GPIO driven peripheral extended the 9% margin case of temperature drift etc... Take a look the AMR of several devices, many have the same boiler plate voltage parameters.

I never stated anyone should operate a device at AMR values rather use them to have an extend margin for errors temperature drift etc. that is common sense.

For instance the AMR minimum input 2.6v is the vendors (guaranteed) voltage the device will respond to a binary High. 

Applying 2.6v to the device input is not at all destructive and will likely drive the first gate even with a voltage applied slightly below that. The AMR expresses a binary High applied below 2.6v may or may not have an effect to enable the first gate into a logic (true) state. We could in fact apply 2 volts for months on end to the very same input shown in the AMR @2.6v and not damage the device. Otherwise it might just assume a binary logic 0 was being applied also not device damaging.

Clearly in respect to the post you both have raided raised Red panic flags over nothing.

We were discussing the Binary High low threshold being 2.6v and somehow you misunderstood 2.6v was inferring the binary low.

Again "Will function down to minimum of 2.6v not any lower". We have been discussing the GPIO port binary high in table 27-7 listed 2.4v minimum and was missing nominal and maximum values.

No shape shifting going on here more like CB1 misunderstood, no big deal yet you start personal attacks for no good reason.

BP101 said:

The reason for marking it answered was the AMR of the GPIO driven peripheral extended the 9% margin case of temperature drift etc...

I don't believe it did.  No other Abs max I have ever read has done so and you've provide no evidence this one has either.  In fact the evidence you did provide (badly formatted) indicated otherwise.

BP101 said:

For instance the AMR minimum input 2.6v is the vendors (guaranteed) voltage the device will respond to a binary High. 

Nope.  I have seen such specification in old devices. They were intended to prevent CMOS latch-up, never to extend the valid input range. That is all in the specifications section. However given your past evidence I doubt that you even have this case.

BP101 said:

I never stated anyone should operate a device at AMR values rather use them to have an extend margin for errors temperature drift etc. that is common sense.

B implies A and it's an absolutely nonsensical use of Abs maximum.  You are very badly misinterpreting what the Abs Max section is telling you and it is a potentially dangerous approach.

You are absolutely wrong about this

If you want to prove us wrong about this you will need to post a properly formatted quote of the Abs Max section of the data sheet complete with footnotes. I am certain you are wrong.

BP101 said:

Perhaps should remove the green question answered since it was not exactly on point.

You have been consistently contradicting everything in that post.

Robert

BTW, when a vendor doesn't desire to test all the parameters they do one of several things

• provide typical values only
• note as not measured, guaranteed by design. Useful for those cases where testing other parameters is sufficient.
• note as measure on a sample basis only

I have seen all three used fairly regularly and there may well be other approaches.

BP101 said:

the Binary low will be no less than 2.6v.

What pray tell - was misunderstood?   Your shape-shifting cannot evade your quotation - frozen here in time - and awarded a ridiculous, "Suggested Answer!"

Have you (really) in a relaxed place & state of mind - re-read - or asked others - to comment upon the meaning of that bp101 quotation?

We suspected that you'd attempt to quibble - evade what you wrote - but the "frozen in time" illogic remains indelible - for all to see!

Recently you add, "you start personal attacks for no good reason."   There is nothing personal!   It is the false claim you make - and represent as, "Suggested Answer" which is (properly) challenged.   As to "good reason" - as past stated - might your illogic be accepted by beginning others - and cause (needless) pain and suffering?   That seems (adequate) reason to alert you to your error - and request that you not let that mistake stand...

In this case the AMR (-.3v) listed for a logic High does not represent the Input extending below COM logic ground. The LDO 3v3 regulator was just an idea to compensate GPIO output for what was believed at the time about the external peripheral. The external peripherals electrical characteristics lists a Binary High 2.9v Min. at the input pin. As you are aware there is no proof or specification in the TM4C datasheet confirming the GPIO port could even reach a 2.9v threshold.

After all the actual GPIO pin only measured 2.98v-2.99v well below the 3v3 VDD rail yet exceeded the 2.9v peripheral minimum by 9%. That ain't great and MPU temperature rise above 25C can reduce that 9% margin even further. 

There is also other describing verbs in this AMR, (exceeding) the absolute values in the table (may) damage the device, both those are non conclusive words.

Stresses (exceeding) in fact means values have to actually go beyond the AMR disclosed values for any (may) damage to occur.

Again that is not suggesting anyone should push the envelope yet the AMR does give leeway for temperature rise above 25c any and all electrical specifications without express temperature derations above or below 25c.

BP101 said:

In this case the AMR (-.3v) listed for a logic High does not represent the Input extending below COM logic ground.

That is absolutely what it means. It is a warning that applying negative voltage to the input may damage it.

This looks like the spec for something like a 1/2 H gate driver. HIN/LIN are pin names.

BP101 said:

Stresses (exceeding) in fact means values have to actually go beyond the AMR disclosed values for any (may) damage to occur.

Data Sheet said:

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

You must stay within the recommended operating conditions to ensure reliability.

BP101 said:

the AMR does give leeway for temperature rise above 25c

Data Sheet said:

T_A = 25C unless otherwise specified

The data sheet directly contradicts you on these assertions.

Lastly, in reference to recommended operating ratings.

Data Sheet said:

Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings

Robert

Robert Adsett said:

BP101

In this case the AMR (-.3v) listed for a logic High does not represent the Input extending below COM logic ground.

That is absolutely what it means. It is a warning that applying negative voltage to the input may damage it.

This looks like the spec for something like a 1/2 H gate driver. HIN/LIN are pin names.

I'd guess a FAN7842 which matches the specs here and the 2V9 input threshold.  Note to others reading this, it uses 10V power supply on its low voltage side.

Robert

BP101 said:

Appears you took that out of context, stated the binary High in the previous sentence

 Hi BP101, I read many of post and I say Robert Has a great patience and time to not tell you about hells you generated.

 Long Time ago due to a defective connector I discovered a set of 300 MSP430 board where burning the smart card where reader was dedicated. On analysis of 3 random picked board over the production I discovered connector where rerouting HIGH vcc of 5V to vdd of processor so processor when pump got activated where powered near 6V, devices got 2 day of this treatment, this proved me device was more and more resistant to maximum rating but forever it is powered on range  @3.3V. None of the 300 board was damaged and correcting connector fault left all board working. They passed a one week burn in and never returned back on 5 year time.

 This show device WAS ( I cannot state was nor it is now) resilient BUT is not to be used as everyday rule of project.

BP101 said:

Stated many times 2.9v was the binary high input voltage and illustrated (2.9v -.3v = 2.6v).

 This again as Robert  wrote many times is not a rule not a good one.

 Remember capacitance is loading output too and this is not an open load!! So if you need guarantee level of minimum 2.9 V as all we do we use some sort of level translation to match devices.

 2.4V min assure you can quite safely drive 5V logic where threshold is near mid of power rail voltage. This is not safe if you load too much output nor if you raise speed, remember you have a fixed slew rate due to capacitance and current drive capability of port.

 So you wrote steady condition Ohm law, did you know about differential equation governing charge of capacitors with fixed current and impedance of capacitors at sine steady state?

 This is not to be forget otherwise your project are aleatory.

Robert Adsett said:

Perversely, it's coffee break diversion. Also a bit of a sanity break if I'm having to work with relay ladder logic.

 Hi Robert, I cannot drink coffee any more, this is a problem due I liked so much.

 I also have to work on VHDL and other problem but one question was in my mind so why not propose the simplest level translator from era of common base emitter collector or drain source or gate?

 A common gate level translator can do the job without wastin a so huge amount of time, using a sot23 or my preferred sc70 or smaller is of no concern where some hig current mosfet are. So common gate level translator is not more effective than lot of post about angel are male or female?

 Source for is LTSpice based, this is the better SPice based tools I found.

SimpleLevelTr.asc.zip