RM48 RTI Clock Source (RCLKSRC), Setting Violation

Hi,

Doing some unit testing on RM48L952 and the RTI module.

We wish to generate a 50MHZ RTI1CLK from a 200MHZ PLL1 (100MHZ VCLK) setting.  We don't use HalCoGen, but refer to the HalCoGen outputs when we get into trouble.

From the GCM tab in HalCoGen we select _RTI1 Pre Src = PLL1, _RTI1 Divider = 2, _RTI1 Post Src = PRE1 to give us a 50MHZ clock.

The resulting code generate is:

    systemREG1->RCLKSRC = (uint32)((uint32)1U << 24U)
                        | (uint32)((uint32)SYS_VCLK << 16U) 
                        | (uint32)((uint32)2U << 8U)  
                        | (uint32)((uint32)SYS_PRE1 << 0U);

This tells us we are generating a 50MHZ clock, BUT the data sheet states, 

NOTE: Important constraint when the RTI clock source is not VCLK
If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI
clock needs to be at least three times slower than the VCLK. This can be achieved by
configuring the RTIxCLK divider in this register. This divider is internally bypassed when the
RTIx clock source is VCLK.

My questions:

1. What are the extra bits set (bit shift 16 and 24) as these don't appear in the data sheet.

2. The data sheet states the RTI CLK must be 3x slower than VCLK. If VCLK = 100MHZ, then the setting of 0 or 1 for the RTI1DIV field of the register RCLKSRC is not valid.  Is this correct?

Thanks

Stomp!.